HLT

HLT stops the logical processor that executes it until something from outside wakes it: an interrupt it accepts, an NMI, an SMI, INIT or RESET. Its home is the operating system’s idle loop, where a core with nothing to run sleeps until the next timer tick or device interrupt instead of spinning. Only that logical processor halts; on a core with two hardware threads, Intel’s optimization manual points out, the other thread then has all of the core’s resources.

Only at CPL 0#

HLT is privileged. At CPL 3 it raises #GP(0) before anything happens: Zen 5 raised #GP, changing nothing, in each case of the Operation section. #GP is a fault, so the saved RIP still points at the HLT (Intel’s Volume 3A, Section 7.5). A user program that wants to wait has the operating system’s blocking calls, or UMWAIT and TPAUSE on processors that have them.

STI then HLT#

An idle loop must check for work with interrupts disabled, or an interrupt arriving between the check and the HLT would be handled first and the processor would then sleep with the work pending. The usual answer is to end the check with sti; hlt: STI enables interrupts only after the next instruction, so no interrupt can be taken between the two, and an interrupt that is already waiting wakes the HLT at once. The handler returns to the instruction after HLT, where the loop checks again.

With IF clear, only an NMI, an SMI, INIT or RESET ends the halt, as AMD’s manual stresses, so cli; hlt parks a processor until one of those arrives; a loop around it keeps it parked after an NMI.

Under a hypervisor#

A guest’s HLT usually leaves the guest: Intel’s VMX can exit on it, and AMD’s SVM has a HLT intercept and an idle-HLT intercept, which exits only if no virtual interrupt is already pending (AMD’s Volume 2). The hypervisor can then run something else on the physical processor until the guest has an interrupt to take. MWAIT, the other way an idle loop can wait, also lets the kernel name a deeper sleep state.

The instruction table of AMD’s Zen 5 guide lists HLT as microcoded.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0:
    fault(GP, 0)
pass                             # halts: no instruction runs until an
                                 # interrupt (with IF set), an NMI, an
                                 # SMI, INIT or RESET wakes it; the
                                 # handler of an interrupt or NMI
                                 # returns to the next instruction
# under a hypervisor, HLT usually leaves the guest, which the
# hypervisor puts to sleep until it has an interrupt for it

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

privileged: CPL 0 only; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More System instructions

• ARPL
• CLTS
• INVD
• INVLPG
• LAR
• LGDT
• LIDT
• LLDT
• LMSW
• LSL
• LTR
• RDMSR
• RDPMC
• RDTSC
• RSM
• SGDT
• SIDT
• SLDT
• SMSW
• STR
• SWAPGS
• VERR
• VERW
• WBINVD
• WRMSR