HRESET

HRESET asks the processor to forget history it keeps about the code running on this logical processor. Intel’s manuals define one kind of it so far: the history behind Intel Thread Director, which watches the running software thread and reports a class for it in IA32_THREAD_FEEDBACK_CHAR, so that the operating system can place the thread on a core type that suits it. A kernel can reset it when it switches threads, so that what the previous thread did does not color the class of the next.

EAX picks, the immediate does not#

The components to reset are the set bits of EAX; bit 0 is Thread Director’s history, and the rest are reserved. The 8-bit immediate is ignored. EAX = 0 makes HRESET a NOP. Three levels have to agree:

• CPUID leaf 07H, subleaf 1, EAX bit 22 says that HRESET exists, or it raises #UD;
• CPUID leaf 20H, EBX, lists the components this processor can reset;
• the kernel enables some of those in the IA32_HRESET_ENABLE MSR, which takes no others, and a bit of EAX that the MSR leaves clear raises #GP(0).

HRESET runs only at CPL 0, or raises #GP(0), and it aborts a TSX transaction. With -mhreset, or an -march such as alderlake, arrowlake or pantherlake (not sapphirerapids), GCC 14 and Clang 23 at -O2 compile _hreset(x) to a move into EAX and hreset 0.

History that goes anyway#

Intel’s manual lists the times the processor resets Thread Director’s history by itself: on entry to and exit from SMM when IA32_DEBUGCTL.FREEZE_WHILE_SMM is set, at GETSEC[SENTER] (on every logical processor) and GETSEC[ENTERACCS], and at INIT or the wait for SIPI. An HRESET also clears the valid bit of IA32_THREAD_FEEDBACK_CHAR, which tells the kernel to ignore the class until the hardware has gathered enough to report one again.

The encoding#

HRESET is F3 0F 3A F0 with the ModRM byte fixed at C0, then the immediate. With a VEX prefix, the same map and opcode is RORX.

AMD’s manual defines no HRESET, and the Zen 5 guest that ran the probe did not report it in CPUID, so this page has no recorded cases.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0:
    fault(GP, 0)
if eax & ~msr[0x17DA]:
    fault(GP, 0)                 # a bit that IA32_HRESET_ENABLE
                                 # leaves clear
pass                             # forgets the history of each
                                 # component that EAX selects: bit 0,
                                 # Thread Director's; imm8 is ignored

Operands

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

privileged: CPL 0 only

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to HRESET, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.