HSUBPD

HSUBPD subtracts within each operand: the low result is the first operand’s low double minus its high one, and the high result the same for the second operand, so hsubpd xmm0, xmm1 gives xmm0[0] - xmm0[1] below and xmm1[0] - xmm1[1] above. HADDPD is the adding form and covers the layout, the NaN order and the SSE3 history; VHSUBPD is the VEX form, working within each 128-bit lane. The differences round and raise exceptions under MXCSR as SUBPD’s do. Zen 5’s recorded cases:

• with MXCSR at 1F80h (round to nearest, all exceptions masked), hsubpd xmm12, xmm6 turned the largest double minus its negative into +infinity, setting OE and PE, while the largest double minus 2.0 rounded back to the largest double;
• with MXCSR at FFC0h (round toward zero, DAZ and FTZ set, all masked), hsubpd xmm12, xmmword ptr [mem] subtracted 1.0 from XMM12’s quiet NaN and 2^-53 from the negative quiet NaN in memory, returned both NaNs unchanged and set no flag.

Both kept bits 511:128 of XMM12 (see mixing SSE and AVX), and the memory form needs an operand aligned to 16 bytes.

In compiled code#

In our builds at -O2 over fixed-size double arrays, r[i] = a[2*i] - a[2*i+1] is one HSUBPD per two results in Clang 23 with -msse3, taking the second vector from memory, and VHSUBPD with a VPERMPD with -mavx2. GCC 14 builds the even and odd vectors instead, from two aligned loads patched with MOVLPD and MOVHPD, and subtracts them with SUBPD. For a single v[0] - v[1], both use UNPCKHPD and SUBSD; only Clang with -Os picks hsubpd xmm0, xmm0. _mm_hsub_pd is HSUBPD in both.

AMD’s latency spreadsheet for Zen 5 gives HSUBPD, like HADDPD, four macro-ops with a latency of 4 cycles and one started every two cycles; SUBPD is one macro-op of 2 cycles, two per cycle.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(2):
    j = 2 * (i % 1)
    if i < 1:
        a = src1.f64[j]
        b = src1.f64[j + 1]
        xmm1.f64[i] = sub(a, b)
    else:
        a = src2.f64[j]
        b = src2.f64[j + 1]
        xmm1.f64[i] = sub(a, b)
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Memory forms

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to HSUBPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE3 instructions

• ADDSUBPD
• ADDSUBPS
• FISTTP
• HADDPD
• HADDPS
• HSUBPS
• LDDQU
• MOVDDUP
• MOVSHDUP
• MOVSLDUP