HSUBPS

HSUBPS subtracts within adjacent pairs of singles, the odd element from the even one: from (a0, a1, a2, a3) and (b0, b1, b2, b3) it makes (a0 - a1, a2 - a3, b0 - b1, b2 - b3), the first operand’s results below. HADDPS adds the same pairs and has more on how compilers use them; HSUBPD is the double form and VHSUBPS works within each 128-bit lane. Each difference rounds under MXCSR as SUBPS’s does. It came with SSE3, part of x86-64-v2; the legacy form keeps bits 128 and up of the register (see SSE and AVX) and needs a memory operand aligned to 16 bytes.

Zen 5’s recorded cases show the order and the rounding:

• With MXCSR at FFC0H (round toward zero, FTZ and DAZ set), hsubps xmm1, xmmword ptr [mem] gave 3 - 2 = 1 and 0.5 - 1.0000001 = -0.50000012 exactly from XMM1, and from memory 0.1 - (-1) as 1.0999999 (3F8CCCCCH, where rounding to nearest gives 3F8CCCCDH) and -0.5 - 1 = -1.5; PE was set.
• Under MXCSR’s default, hsubps xmm0, xmm13 gave 1 - infinity = -infinity and infinity - 0 = infinity, and from XMM13 -2^-24 - (-infinity) and infinity - (-0), both infinity, with no flag.

Only one order#

There is no reversed form. In our builds at -O2 with -march=x86-64-v2, Clang 23 compiles r[i] = a[2*i] - a[2*i+1] to one HSUBPS per four results, reading the second operand from memory, but r[i] = a[2*i+1] - a[2*i] to two SHUFPS that separate the even and odd elements and a SUBPS; GCC 14 uses the shuffles and SUBPS for both. AMD’s spreadsheet for Zen 5 lists HSUBPS like HADDPS: four macro-ops, a latency of 4 cycles and one every two cycles.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = xmm1.read()  # xmm1 as it was
for i in range(4):
    j = 2 * (i % 2)
    if i < 2:
        a = src1.f32[j]
        b = src1.f32[j + 1]
        xmm1.f32[i] = sub(a, b)
    else:
        a = src2.f32[j]
        b = src2.f32[j + 1]
        xmm1.f32[i] = sub(a, b)
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Memory forms

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to HSUBPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE3 instructions

• ADDSUBPD
• ADDSUBPS
• FISTTP
• HADDPD
• HADDPS
• HSUBPD
• LDDQU
• MOVDDUP
• MOVSHDUP
• MOVSLDUP