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Instruction

IBHF

Indirect branch history fence: in ring 0 with BHI_DIS_S set, stops older branch history from steering later indirect branches; a no-op without BHI_CTRL.

Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of IBHF that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
IBHF IBHFF3 REX.W 0F 1E F8BHI_CTRL

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
IBHF

BHI_CTRL
CPUID.(EAX=07H,ECX=2):EDX[4] BHI_CTRL

Arrow Lake, Panther Lake, Nova Lake

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel: Branch History Injection and Intra-mode Branch Target Injection

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.