IDIV

IDIV is the signed counterpart of DIV: it divides rDX:rAX (AX for bytes) by its operand and leaves the quotient in rAX (AL) and the remainder in rDX (AH). The quotient is rounded toward zero and the remainder takes the sign of the dividend, which is what C’s / and % require: -7 / 2 gives -3 with remainder -1, and 7 / -2 gives -3 with remainder 1.

The upper half holds the sign#

The dividend is twice as wide as the divisor, so dividing one register by another needs an upper half filled with copies of the lower half’s sign bit. GCC 14 and Clang 23 at -O2 emit CQO before idiv rsi and CDQ before idiv esi. The xor edx, edx that prepares DIV is wrong here: with RDX = 0 and RAX = -7, the dividend is 2^64 - 7, and IDIV by 2 returns 9,223,372,036,854,775,804 instead of -3, with no fault to show it. Intel’s optimization manual allows the XOR in place of CDQ only when the dividend is known to be positive (Section 3.5.1.1).

Two divide errors#

IDIV raises #DE for a divisor of 0 and for a quotient that does not fit in rAX (AL for bytes). With a sign-extended dividend, the second case has one instance per size: the most negative number divided by -1, whose quotient is one too large (2^63 for 64 bits). Since IDIV computes both results at once, LONG_MIN % -1 faults too, although its remainder, 0, would fit. For bytes the dividend is all of AX, so -128 / -1 overflows AL. C leaves these cases undefined, and neither compiler checks for them. In the cases recorded on Zen 5, dividing 7 by 0, LONG_MIN by -1 and INT_MIN by -1 each raised #DE at the IDIV, which Linux 7.3 hands to the program as SIGFPE with si_code FPE_INTDIV and si_addr pointing at the instruction.

Narrowing 64-bit divisions#

Clang 23 puts a test before a 64-bit IDIV: it ORs the two operands and, when bits 63:32 of the result are zero, so that both are nonnegative 32-bit values, runs xor edx, edx and the 32-bit div esi instead. GCC 14 emits the CQO and IDIV alone. Division by a constant uses neither: both compilers multiply by a scaled reciprocal, as for DIV.

In the optimization guide

What the optimization guide says about IDIV, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Bulldozer to Excavator

• Integer execution: DIV and IDIV are microcoded, and their time grows with the width of the dividend’s value on Bulldozer and of the quotient’s from Piledriver on, up to 76 and 72 cycles for 64-bit operands, so a division by a constant is best done by multiplying. sources differ

Golden Cove and Raptor Cove

• Integer execution: Integer division runs on port 1; LLVM’s models give a 32-bit DIV 15 cycles and a 64-bit one 18, the latter three micro-ops that keep port 1 busy for three cycles.

Haswell and Broadwell

• Integer execution and bypass: A 64-bit integer divide is much slower than a 32-bit one, so LLVM, tuning for Haswell or Broadwell, uses the 32-bit divide when both 64-bit operands turn out positive and below 2^32. sources differ

Ice Lake to Rocket Lake

• Integer execution: A new integer divider on port 1 makes DIV and IDIV much faster than on Skylake, in latency and in throughput; neither Intel nor Agner Fog gives numbers. sources differ

Jaguar and Puma

• Integer execution: The radix-4 divider produces two quotient bits a cycle: AMD’s spreadsheet gives DIV and IDIV at most 25 cycles with 32-bit operands and 41 with 64-bit ones, ending early when the quotient is small. sources differ

Sandy Bridge and Ivy Bridge

• Integer and vector execution: One divider, on port 0, serves integer division and also the square root and floating-point division operations, so only one of them runs at a time; LLVM’s model gives an 8-, 16-, 32- or 64-bit integer divide the same 25-cycle latency and a throughput of one every 10 cycles.

Silvermont to Goldmont Plus

• Out-of-order and in-order execution: Division is microcoded and slow on Silvermont, up to 135 cycles at 64 bits; Goldmont takes 11 to 41. sources differ

Skylake to Cooper Lake

• Integer execution: Integer division is slow: LLVM’s models give a 64-bit DIV 76 cycles and 32 micro-ops and a 64-bit IDIV 102 cycles, against 18 on Golden Cove.

Tremont

• Integer execution: Three ALU ports run simple integer operations, three a cycle; shifts go to port 00 only, and multiplication, division, popcnt, crc32 and the bit operations to port 01 only.

Zen and Zen+

• Integer execution: The divider, on ALU 2, yields two bits of the quotient a cycle: AMD’s spreadsheet gives a 64-bit DIV 41 cycles and a 32-bit one 25, as LLVM’s model does.

Zen 2

• Integer execution: The divider produces two bits of the quotient a cycle, so division is slow: AMD’s spreadsheet gives a 64-bit DIV 41 cycles and a 32-bit one 25, as LLVM’s model does, far more than on Zen 3.

Zen 3

• Integer execution: Division runs on ALU 0 and takes about 8 cycles plus 1 for every 9 bits of the quotient, and a typical 64-bit division can start every 8 cycles. sources differ

Zen 4

• Integer execution: xor edx, edx before DIV, or CDQ or CQO before IDIV, with the same operand size and a divisor in a register other than rDX, saves a macro-op: the pair is dispatched as one fewer.
• Integer execution: Division takes about 8 cycles plus 1 for every 9 bits of the quotient, and a typical 64-bit division can start every 8 cycles. sources differ

Zen 5

• Integer execution: Division takes about 8 cycles plus 1 for every 9 bits of the quotient, and a typical 64-bit division can start every 8 cycles.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

d = signed(src)
if d == 0:
    fault(DE)                    # a divide by zero
if OSIZE == 8:
    n = signed(ax)               # the dividend: AX, DX:AX, EDX:EAX or
else:                            # RDX:RAX, signed
    n = signed(rDX) << OSIZE | rAX
q = abs(n) // abs(d)             # the quotient rounds toward zero
if (n < 0) != (d < 0):
    q = -q
big = 1 << (OSIZE - 1)
if not -big <= q < big:
    fault(DE)                    # the quotient does not fit in rAX: as
                                 # for the smallest number divided by -1
r = n - q * d                    # the remainder has the dividend's sign
if OSIZE == 8:
    al = q
    ah = r
else:                            # EAX and EDX: bits 63:32 cleared
    rAX = q
    rDX = r
if not nf:                       # NF=1 (APX) leaves the flags as they were
    of = sf = zf = af = pf = cf = UNDEFINED

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• CBW
• CDQ
• CDQE
• CLC
• CLD
• CLI
• CMC
• CMP
• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• DIV
• ENTER
• IMUL
• IN
• INC
• INS
• INT
• INT1
• INT3
• INTO
• IRET
• Jcc
• JCXZ
• JECXZ
• JMP
• JRCXZ
• LDS
• LEA
• LEAVE
• LES
• LFS
• LGS

All 109 General-purpose instructions

More APX instructions

• ADOX
• AND
• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI
• MOVRS
• MUL
• MULX
• NEG
• NOT

All 88 APX instructions