Instruction
IDIV
Divides a signed double-width dividend in rDX:rAX (AX for bytes) by the operand into quotient and remainder; APX adds a form that keeps the flags.
- Extensions
- Forms
- 12 (4 Legacy, 8 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
IDIV m8
IDIV_MEMb | F6 /7 | Base instruction set |
IDIV r8
IDIV_GPR8 | F6 /7 | Base instruction set |
IDIV m16/32/64
IDIV_MEMv | F7 /7 | Base instruction set |
IDIV r16/32/64
IDIV_GPRv | F7 /7 | Base instruction set |
IDIV r8
IDIV_GPR8i8_APX | EVEX.LLZ.NP.MAP4.WIG F6 /7 | APX_F |
IDIV m8
IDIV_MEMi8_APX | EVEX.LLZ.NP.MAP4.WIG F6 /7 | APX_F |
IDIV r8 NF
IDIV_GPR8i8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG F6 /7 NF=1 | APX_F + APX_NCI_NDD_NF |
IDIV m8 NF
IDIV_MEMi8_APX_N3 | EVEX.LLZ.NP.MAP4.WIG F6 /7 NF=1 | APX_F + APX_NCI_NDD_NF |
IDIV r16/32/64
IDIV_GPRv_APX | EVEX.LLZ.NP.MAP4.SCALABLE F7 /7 | APX_F |
IDIV m16/32/64
IDIV_MEMv_APX | EVEX.LLZ.NP.MAP4.SCALABLE F7 /7 | APX_F |
IDIV r16/32/64 NF
IDIV_GPRv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE F7 /7 NF=1 | APX_F + APX_NCI_NDD_NF |
IDIV m16/32/64 NF
IDIV_MEMv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE F7 /7 NF=1 | APX_F + APX_NCI_NDD_NF |
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
I86 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
APX_F | APX_F | Nova Lake, Diamond Rapids |
APX_F_N3 | APX_F + APX_NCI_NDD_NF | Nova Lake, Diamond Rapids |
More General-purpose instructions
- CBW
- CDQ
- CDQE
- CLC
- CLD
- CLI
- CMC
- CMP
- CMPS
- CMPXCHG
- CMPXCHG8B
- CPUID
- CQO
- CWD
- CWDE
- DAA
- DAS
- DEC
- DIV
- ENTER
- IMUL
- IN
- INC
- INS
- INT
- INT1
- INT3
- INTO
- IRET
- Jcc
- JCXZ
- JECXZ
- JMP
- JRCXZ
- LDS
- LEA
- LEAVE
- LES
- LFS
- LGS
All 109 General-purpose instructions
More APX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
- Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.