x86-64.net

Instruction

IMUL

Multiplies signed integers in one-, two- and three-operand forms; APX adds new-destination, flag-preserving and zero-upper immediate forms.

Extensions
Forms
36 (10 Legacy, 26 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of IMUL that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
IMUL m8 IMUL_MEMbF6 /5Base instruction set
IMUL r8 IMUL_GPR8F6 /5Base instruction set
IMUL m16/32/64 IMUL_MEMvF7 /5Base instruction set
IMUL r16/32/64 IMUL_GPRvF7 /5Base instruction set
IMUL r16/32/64, m16/32/64, imm16/32 IMUL_GPRv_MEMv_IMMz69 /r iw/idBase instruction set
IMUL r16/32/64, r16/32/64, imm16/32 IMUL_GPRv_GPRv_IMMz69 /r iw/idBase instruction set
IMUL r16/32/64, m16/32/64, imm8 IMUL_GPRv_MEMv_IMMb6B /r ibBase instruction set
IMUL r16/32/64, r16/32/64, imm8 IMUL_GPRv_GPRv_IMMb6B /r ibBase instruction set
IMUL r16/32/64, m16/32/64 IMUL_GPRv_MEMv0F AF /rBase instruction set
IMUL r16/32/64, r16/32/64 IMUL_GPRv_GPRv0F AF /rBase instruction set
IMUL r16/32/64, r16/32/64, imm16/32 IMUL_GPRv_GPRv_IMMz_APXEVEX.LLZ.NP.MAP4.SCALABLE 69 /r iw/idAPX_F
IMUL r16/32/64, m16/32/64, imm16/32 IMUL_GPRv_MEMv_IMMz_APXEVEX.LLZ.NP.MAP4.SCALABLE 69 /r iw/idAPX_F
IMUL r16/32/64, r16/32/64, imm16/32 ZU NF optional IMUL_GPRv_GPRv_IMMz_APX_N3_ZUEVEX.LLZ.NP.MAP4.SCALABLE 69 /r iw/id ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
IMUL r16/32/64, m16/32/64, imm16/32 ZU NF optional IMUL_GPRv_MEMv_IMMz_APX_N3_ZUEVEX.LLZ.NP.MAP4.SCALABLE 69 /r iw/id ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
IMUL r16/32/64, r16/32/64, imm16/32 NF IMUL_GPRv_GPRv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 69 /r iw/id NF=1APX_F + APX_NCI_NDD_NF
IMUL r16/32/64, m16/32/64, imm16/32 NF IMUL_GPRv_MEMv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 69 /r iw/id NF=1APX_F + APX_NCI_NDD_NF
IMUL r16/32/64 IMUL_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE F7 /5APX_F
IMUL m16/32/64 IMUL_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE F7 /5APX_F
IMUL r16/32/64 NF IMUL_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F7 /5 NF=1APX_F + APX_NCI_NDD_NF
IMUL m16/32/64 NF IMUL_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F7 /5 NF=1APX_F + APX_NCI_NDD_NF
IMUL r16/32/64, r16/32/64, imm8 IMUL_GPRv_GPRv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 6B /r ibAPX_F
IMUL r16/32/64, m16/32/64, imm8 IMUL_GPRv_MEMv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 6B /r ibAPX_F
IMUL r16/32/64, r16/32/64, imm8 ZU NF optional IMUL_GPRv_GPRv_IMM8_APX_N3_ZUEVEX.LLZ.NP.MAP4.SCALABLE 6B /r ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
IMUL r16/32/64, m16/32/64, imm8 ZU NF optional IMUL_GPRv_MEMv_IMM8_APX_N3_ZUEVEX.LLZ.NP.MAP4.SCALABLE 6B /r ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
IMUL r16/32/64, r16/32/64, imm8 NF IMUL_GPRv_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 6B /r ib NF=1APX_F + APX_NCI_NDD_NF
IMUL r16/32/64, m16/32/64, imm8 NF IMUL_GPRv_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 6B /r ib NF=1APX_F + APX_NCI_NDD_NF
IMUL r16/32/64, r16/32/64 IMUL_GPRv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE AF /rAPX_F
IMUL r16/32/64, m16/32/64 IMUL_GPRv_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE AF /rAPX_F
IMUL r16/32/64, r16/32/64 NF IMUL_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE AF /r NF=1APX_F + APX_NCI_NDD_NF
IMUL r16/32/64, m16/32/64 NF IMUL_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE AF /r NF=1APX_F + APX_NCI_NDD_NF
IMUL r16/32/64, r16/32/64, r16/32/64 NDD NF optional IMUL_GPRv_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE AF /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
IMUL r16/32/64, r16/32/64, m16/32/64 NDD NF optional IMUL_GPRv_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE AF /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
IMUL r8 IMUL_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG F6 /5APX_F
IMUL m8 IMUL_MEMi8_APXEVEX.LLZ.NP.MAP4.WIG F6 /5APX_F
IMUL r8 NF IMUL_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG F6 /5 NF=1APX_F + APX_NCI_NDD_NF
IMUL m8 NF IMUL_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG F6 /5 NF=1APX_F + APX_NCI_NDD_NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
I186

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.