INC

INC adds 1 to its operand and sets the flags as add x, 1 would, with one exception: CF keeps its value. OF is set only when the largest positive number wraps to the smallest negative one, and ZF when the operand wraps to 0, so INC can still end a loop or detect a wrap.

Why CF is left alone#

CF often holds data that a loop carries from one step to the next. In a multi-word addition, each ADC passes its carry to the next, and the loop must step its pointers and count its words without disturbing CF. Intel’s Optimization Reference Manual shows such a loop for 1024-bit numbers (Example 3-26): LEA advances the pointers, DEC and JNZ count, and neither touches CF. The manual adds that this form is the faster one on Sandy Bridge, and that earlier processors stall on it.

The cost of a partial write#

Because INC writes some flags and keeps another, an instruction that then reads CF together with the others depends on two earlier instructions. Intel’s manual describes this as a partial flag register stall on older processors and as an extra micro-op in Sandy Bridge, and still recommends few INC and DEC instructions before those that write the flags conditionally, such as shifts by CL (Section 3.5.2.5). Fusion with a following jump is narrower too: Intel’s Table 3-1 (Sandy Bridge) and Table 3-2 (Haswell) fuse INC only with the equal and signed conditions, never with those that read CF, while AMD’s guide lists INC among the instructions that fuse on Zen 5 (Section 2.9.3).

In compiled code#

GCC 14 and Clang 23 differ at -O2: for ++*p on a long, GCC emits add qword ptr [rdi], 1, Clang inc qword ptr [rdi], and for an atomic increment GCC uses lock add and Clang lock inc. Both use lea rax, [rdi + 1] when the result goes to another register.

In 64-bit mode the one-byte encodings 40h to 47h are REX prefixes, so INC takes FF /0 (FE /0 for bytes): inc eax is 2 bytes, one fewer than add eax, 1. DEC is the same story with 1 subtracted.

In the optimization guide

What the optimization guide says about INC, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Front end

• Macro-fusion: Intel’s cores since Sandy Bridge (Skylake) fuse test and and with any conditional branch; cmp, add and sub with branches on the equal, unsigned and signed comparisons, but not on the sign, parity or overflow flag alone; and inc and dec only with branches on equality and the signed comparisons.
• Macro-fusion: AMD’s Zen 3 to Zen 5 fuse more: cmp, test, add, sub, and, or, xor, inc and dec with any conditional branch, except that on Zen 3 and Zen 4 inc and dec do not fuse with a branch that reads the carry flag, which Intel’s cores do not fuse either (Zen 5, Zen 4, Zen 3). sources differ

Out of order

• Partial register and flag writes: Some instructions write only part of the flags: inc and dec leave the carry flag as it was, and bt leaves the zero flag.

Silvermont to Goldmont Plus

• Out-of-order and in-order execution: A branch on the flags of inc or dec costs a cycle more than one on add, sub or cmp.

Skylake to Cooper Lake

• Front end: test and and fuse with any following conditional jump; cmp, add and sub with the jumps on equality and on the unsigned and signed comparisons, but not with js, jp or jo and their inverses; inc and dec only with those on equality and the signed comparisons.

Tremont

• Integer execution: LLVM prefers add and sub to inc and dec on Tremont, where a partial flags write costs a cycle.

Zen 3

• Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, unless it carries a displacement together with an immediate, addresses relative to RIP or makes the pair longer than 15 bytes; inc and dec do not fuse with a branch on the carry flag, and jrcxz never fuses.

Zen 4

• Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, unless it carries a displacement together with an immediate, addresses relative to RIP or makes the pair longer than 15 bytes; inc and dec do not fuse with a branch on the carry flag.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()                  # with LOCK: one atomic read-modify-write
r = low(a + 1)
if not nf:                       # NF=1 (APX) leaves the flags as they were
    of = r == 1 << (OSIZE - 1)   # the largest positive number wrapped
    sf = msb(r)
    zf = r == 0
    af = (a & 0xF) == 0xF        # a carry out of bit 3
    pf = parity(r)
    # CF keeps its value, unlike after ADD dest, 1
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

a = src.read()
r = low(a + 1)
if not nf:                       # NF=1 leaves the flags as they were
    of = r == 1 << (OSIZE - 1)   # the largest positive number wrapped
    sf = msb(r)
    zf = r == 0
    af = (a & 0xF) == 0xF        # a carry out of bit 3
    pf = parity(r)
    # CF keeps its value
dest.write(r)                    # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

Attributes

What else XED records about the forms. How to read.

Legacy memory forms without LOCK

accepts a LOCK prefix

LOCK forms

locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• CLC
• CLD
• CLI
• CMC
• CMP
• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• DIV
• ENTER
• IDIV
• IMUL
• IN
• INS
• INT
• INT1
• INT3
• INTO
• IRET
• Jcc
• JCXZ
• JECXZ
• JMP
• JRCXZ
• LDS
• LEA
• LEAVE
• LES
• LFS
• LGS
• LODS
• LOOP
• LOOPE

All 109 General-purpose instructions

More APX instructions

• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI
• MOVRS
• MUL
• MULX
• NEG
• NOT
• OR
• PDEP

All 88 APX instructions