x86-64.net

Instruction

INC

Adds one to an operand without changing the carry flag; APX adds three-operand forms and forms that leave the flags unchanged.

Extensions
Forms
19 (7 Legacy, 12 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of INC that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
INC m8 INC_MEMbFE /0Base instruction set
INC r8 INC_GPR8FE /0Base instruction set
INC m16/32/64 INC_MEMvFF /0Base instruction set
INC r16/32/64 INC_GPRv_FFr0FF /0Base instruction set
INC r16/32/64 not in 64-bit mode INC_GPRv_4040+rBase instruction set
LOCK INC m8 INC_LOCK_MEMbFE /0Base instruction set
LOCK INC m16/32/64 INC_LOCK_MEMvFF /0Base instruction set
INC r8 INC_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG FE /0APX_F
INC m8 INC_MEMi8_APXEVEX.LLZ.NP.MAP4.WIG FE /0APX_F
INC r8 NF INC_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG FE /0 NF=1APX_F + APX_NCI_NDD_NF
INC m8 NF INC_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG FE /0 NF=1APX_F + APX_NCI_NDD_NF
INC r8, r8 NDD NF optional INC_GPR8i8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG FE /0 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
INC r8, m8 NDD NF optional INC_GPR8i8_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG FE /0 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
INC r16/32/64 INC_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE FF /0APX_F
INC m16/32/64 INC_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE FF /0APX_F
INC r16/32/64 NF INC_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE FF /0 NF=1APX_F + APX_NCI_NDD_NF
INC m16/32/64 NF INC_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE FF /0 NF=1APX_F + APX_NCI_NDD_NF
INC r16/32/64, r16/32/64 NDD NF optional INC_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE FF /0 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
INC r16/32/64, m16/32/64 NDD NF optional INC_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE FF /0 ND=1 NF=0/1APX_F + APX_NCI_NDD_NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.