x86-64.net

Instruction

INS

Reads a byte, word or doubleword from the I/O port in DX into memory at [RDI] and steps RDI; REP repeats it RCX times.

Extensions
Mnemonics
INS, INSB, INSW, INSD
Forms
6 (6 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of INS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
INSB INSB6CBase instruction set
INSW INSW66 6DBase instruction set
INSD INSD6D
REX.W 6D		Base instruction set
REP INSB REP_INSBF3 6C
F2 6C		Base instruction set
REP INSW REP_INSW66 F3 6D
66 F2 6D		Base instruction set
REP INSD REP_INSDF3 6D
F3 REX.W 6D
F2 6D
F2 REX.W 6D		Base instruction set

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I186

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
I386

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.