INSERTPS instruction (SSE4.1)

INSERTPS writes one single into an XMM register and can clear any of its four elements in the same step. The immediate has three fields:

bits 7:6 pick the element of the source register to take; a memory source is a single four-byte load, and these bits are ignored;
bits 5:4 pick the element of the destination that receives it;
bits 3:0 name the elements to set to zero afterwards.

The zeroing comes last and wins: on Zen 5, insertps xmm4, dword ptr [mem], 0C9h put the loaded value into element 0, then cleared elements 0 and 3, so the load left no trace. Elements neither written nor cleared keep their values, which makes the old destination an input, as for PINSRD, the integer counterpart. Unlike MOVSS, it can move a single between any two positions of two registers without shuffling them first.

Building vectors

With -msse4.1, GCC 14 and Clang 23 at -O2 both compile v[2] = a, on a vector of four floats, to insertps xmm0, xmm1, 20h. Building a whole vector from four scalars, _mm_setr_ps(a, b, c, d), shows two styles: Clang inserts b, c and d into a with three INSERTPS, one after another, while GCC joins pairs with two UNPCKLPS and a MOVLHPS, whose first two steps do not depend on each other. For _mm_setr_ps(a, b, c, 0) Clang sets zeroing bits in the same instructions (1Ch, then 28h). Loading a three-float struct, GCC inserts the middle field straight from memory and Clang uses MOVSD and two SHUFPS.

Intel’s optimization manual suggests INSERTPS for packing the results of several DPPS dot products into one register (Section 7.6.1). AMD’s Zen 5 guide lists it as one macro-op with a latency of one cycle, on any of the four vector pipes.

Other forms

The intrinsic _mm_insert_ps(a, b, imm) compiles to INSERTPS in both compilers, and to VINSERTPS once AVX is enabled. VINSERTPS, in VEX and EVEX forms, takes the other elements from a separate register and clears the bits above 127; it exists for XMM registers only. EXTRACTPS goes the other way.

Forms

Every encoding of INSERTPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`INSERTPS xmm, m32, imm8` INSERTPS_XMMps_MEMd_IMMb	`66 0F 3A 21 /r ib`	SSE4.1
`INSERTPS xmm, xmm, imm8` INSERTPS_XMMps_XMMps_IMMb	`66 0F 3A 21 /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Insert: imm8[7:6] picks a single of xmm2, imm8[5:4] where it goes in xmm1, and imm8[3:0] which singles are zeroed; the rest of the result comes from xmm1.

With m32, the single is the one in memory, and imm8[7:6] is not used. Example: imm8 = 0x9A.

With imm8 = 0x9A, result singles 3 to 0: 0, a2, 0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if src2.is_memory:
    x = src2.d[0]
else:
    x = src2.d[imm8 >> 6]
for i in range(4):
    if imm8 >> i & 1:
        xmm1.d[i] = 0
    elif i == imm8 >> 4 & 3:
        xmm1.d[i] = x
    # else: xmm1.d[i] keeps its value
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`INSERTPS xmm, xmm/m32, imm8`
`xmm`	explicit	read, write
`xmm/m32`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to INSERTPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_insert_ps` `__m128 _mm_insert_ps(__m128 X, __m128 Y, const int N)`	`INSERTPS xmm, xmm, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Building vectors#

Other forms#