INT instruction (General-purpose)

INT n raises a software interrupt: it delivers vector n, 0 to 255, through the interrupt descriptor table as if a device had requested it, with the address of the next instruction as the return point, so the handler’s IRET resumes after the INT. Unlike a device’s interrupt, it ignores IF, and INT 2 reaches the NMI handler without the processor treating it as an NMI (Intel’s Volume 3).

The gate decides who may use it

Every gate has a privilege level, and INT n from code less privileged than that raises #GP, with an error code naming the gate (8n + 2). An operating system thus opens only the vectors it means user code to raise. On the Linux host of the probe, Zen 5 at CPL 3 reached #BP with INT 3 (CD 03) and #OF with INT 4, and recorded #GP for each of the other vectors tried, among them 0, 1, 2, 8, 13, 14, 32, 129 and 255. Through such a gate, int 0x80 is the system call of 32-bit Linux programs, as the system call conventions describe; 64-bit code uses SYSCALL.

Not the same as a real exception

INT n with the vector of an exception runs that exception’s handler, but not with that exception’s frame: it never pushes an error code. A handler of #GP (13), #PF (14) or #DF (8) that is reached by INT n would take the return address for an error code; Intel’s manual warns that such a handler may not work correctly. INT n is also always a trap, returning past the instruction, where #GP and #PF are faults.

Its kin

INT3 (CC) is the one-byte breakpoint, which the assemblers emit for int 3; CD 03 reaches the same vector but takes two bytes. INT1 (F1) raises #DB through a gate of any privilege level, and INTO, which raised #OF when OF was set, does not exist in 64-bit mode. With FRED enabled, INT n is delivered as an event of type 4, software interrupt, apart from both the exceptions and external interrupts. AMD’s Zen 5 guide lists INT as microcoded.

Forms

Every encoding of INT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`INT imm8` INT_IMMb	`CD ib`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`imm8`
Sandy Bridge	100 / 0.33p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake, Alder Lake, Sapphire Rapids	100 / 0.25p0156
Lunar Lake	100 / 0.17p012345
Bonnell	127 / 63.5p01
Silvermont	100 / 1FPC0
Piledriver	100 / 0.5EX0 EX1
Zen, Zen 2	100 / 0.25
Zen 3, Zen 4	100 / 25ALU0 ALU1 ALU2 ALU3
Jaguar	100 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = vector.read()                # 0 to 255
g = gate(n)                      # IDT entry n; past the IDT's limit,
                                 # #GP(8n + 2)
if g >> 40 & 0xF not in (0xE, 0xF):
    fault(GP, 8 * n + 2)         # not an interrupt or trap gate
if g >> 45 & 3 < CPL:
    fault(GP, 8 * n + 2)         # the gate's DPL: the least privileged
                                 # level whose software may use it
if g >> 47 & 1 == 0:
    fault(NP, 8 * n + 2)         # not present
interrupt(n)                     # the handler, with no error code for
                                 # any vector: INT 13 pushes none,
                                 # where #GP pushes one
# a trap: the handler returns to the next instruction. CD 03 is INT
# 3, with the same steps as INT3 in 64-bit mode

Run on AMD Zen 5 (EPYC 9645): 18 cases. Every one raised an exception, at CPL 3, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`INT imm8`
`imm8`	explicit	read
`rIP`	implicit	write
`RFLAGS`	implicit	read, write

Flags

T tested, M modified, 0 cleared; blank: not affected. How to read.

IF	TF	AC	IOPL	NT	RF	VM	VIF
All forms
M	0	M	T	M	0	TM	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

The gate decides who may use it#

Not the same as a real exception#

Its kin#