INT1 instruction (General-purpose)

INT1 is the one-byte opcode F1, which also goes by the name ICEBP. It raises a debug exception, #DB (vector 1), as a trap: the handler sees RIP pointing past it. Unlike a #DB from a breakpoint or single-stepping, it sets no bit of DR6 to say why. Intel’s manual notes that hardware vendors may use it for their debugging tools, and recommends INT3 for software breakpoints; INT3’s page shows how debuggers use that.

Not the same as INT 1

INT with an operand of 1 (CD 01) reaches the same vector through a different check. INT n and INT3 fault with #GP when the gate’s privilege level is below the current one; INT1 skips that check, so it reaches the #DB handler from any privilege level, the way the hardware’s own debug exceptions do. On the Linux host of the probe, Zen 5 at CPL 3 recorded #DB for each INT1 case of the Operation section, while INT 1 raised #GP there, as INT’s page shows: the gate admits only the kernel.

How the processor files it

INT1 is not counted as a software interrupt:

with FRED, it is delivered as event type 5, a privileged software exception, where INT3 is type 6 and INT n type 4;
in an error code that a fault during its delivery pushes, the EXT bit is set, as for an external event (Intel’s Volume 3);
AMD’s manual counts it, with INT3 and INTO, among exceptions rather than software interrupts in EXITINTINFO, and gives it its own SVM intercept, ICEBP, since the #DB intercept does not catch it.

AMD’s Zen 5 guide lists ICEBP as microcoded.

Forms

Every encoding of INT1 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`INT1` INT1	`F1`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

g = gate(1, 1)                   # EXT set in the error codes: INT1
                                 # counts as an event from outside the
                                 # program; past the limit, #GP(11)
if g >> 40 & 0xF not in (0xE, 0xF):
    fault(GP, 11)                # 8 * 1 + 2 + 1
if g >> 47 & 1 == 0:
    fault(NP, 11)
interrupt(1)                     # #DB, a trap, through a gate of any
                                 # DPL: INT1 has no DPL check, where
                                 # INT 1 (CD 01) has
# DR6 gets no bit for it. Intel's manual leaves F1 to hardware
# debuggers, and names it ICEBP too

Run on AMD Zen 5 (EPYC 9645): 3 cases. Every one raised an exception, at CPL 3, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`INT1`
`rIP`	implicit	write

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Not the same as INT 1#

How the processor files it#