INTO

INTO raises the overflow exception, #OF, vector 4, when OF is set, and does nothing when it is clear. Placed after a signed addition or subtraction, it turns an overflow into a call of the #OF handler. Unlike a fault, #OF from INTO is a trap: the handler’s IRET returns to the instruction after INTO, so a handler that returns lets the program go on with the wrapped result.

Delivery is that of INT n with vector 4, with the same check of the gate’s privilege level: INTO from code less privileged than the gate raises #GP. It differs from INT 4 (CD 04) in three ways that Intel’s manual lists: in virtual-8086 mode it ignores IOPL, it bypasses the redirection of interrupts that the virtual-8086 mode extensions provide, and with FRED it is delivered as a software exception, event type 6, where INT 4 is a software interrupt, type 4. Intel’s ordering rule for INT n, that later instructions wait until all earlier ones have completed, covers INTO only when OF is set.

Not in 64-bit mode#

Opcode CE raises #UD in 64-bit mode, so the fixture has no case for INTO: the probe runs there and lists it as not run. In compatibility mode it runs, and #OF is then delivered through the 16-byte gates of the long-mode IDT, as every interrupt in long mode is (AMD’s Volume 2). In 64-bit code a JNO over an INT 4 does the same job: the gate of vector 4 on the Linux host admits user code, as the recorded int 0x4 at CPL 3 reached #OF on Zen 5. Compilers check for overflow with a branch: in our builds, __builtin_add_overflow followed by __builtin_trap() becomes an ADD, a JO and a UD2 in GCC 14 at -O2 with -m32. GNU as 2.44 and Clang 23 refuse into in 64-bit code.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if of:                           # else nothing happens
    g = gate(4)                  # IA-32e mode's IDT
    if g >> 40 & 0xF not in (0xE, 0xF):
        fault(GP, 34)            # 8 * 4 + 2
    if g >> 45 & 3 < CPL:
        fault(GP, 34)            # the gate's DPL, as for INT n
    if g >> 47 & 1 == 0:
        fault(NP, 34)
    interrupt(4)                 # #OF, a trap: the handler returns to
                                 # the next instruction
# in 64-bit mode CE is not INTO: it raises #UD

Operands

Flags

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• DIV
• ENTER
• IDIV
• IMUL
• IN
• INC
• INS
• INT
• INT1
• INT3
• IRET
• Jcc
• JCXZ
• JECXZ
• JMP
• JRCXZ
• LDS
• LEA
• LEAVE
• LES
• LFS
• LGS
• LODS
• LOOP
• LOOPE
• LOOPNE
• LSS
• MOV
• MOVS
• MOVSX

All 109 General-purpose instructions