INVD instruction (System)

Forms

Every encoding of INVD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`INVD` INVD	`0F 08`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0:
    fault(GP, 0)
if msr_exists(0x151) and msr[0x151] & 1:
    fault(GP, 0)                 # BIOS_DONE (Intel's, where CPUID
                                 # 7H.1H:EAX[30] says): once the
                                 # firmware is done, no more INVD
pass                             # drops every line of the caches,
                                 # modified ones too, without writing
                                 # them back, and tells the external
                                 # caches to do the same
# Intel's processors also refuse INVD (#GP(0)) while the memory of
# SGX enclaves or of TDX's SEAM range is protected

Run on AMD Zen 5 (EPYC 9645): 2 cases. Every one raised an exception, at CPL 3, where the probe runs.

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: privileged: CPL 0 only; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I486REAL` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

INVD