Instruction
INVEPT
Invalidates cached translations derived from a VMX guest's extended page tables, for one EPT context or all of them.
- Extensions
- Forms
- 3 (2 Legacy, 1 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
INVEPT r64, m128 64-bit mode only
INVEPT_GPR64_MEMdq | 66 0F 38 80 /r | VMX |
INVEPT r32, m128 not in 64-bit mode
INVEPT_GPR32_MEMdq | 66 0F 38 80 /r | VMX |
INVEPT r64, m128
INVEPT_GPR64i64_MEMi128_APX | EVEX.LLZ.F3.MAP4.WIG F0 /r | APX_F + VMX |
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
VTX | VMX | Core (Merom, Conroe), Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Bonnell, Saltwell, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2 |
APX_F_VMX | APX_F + VMX | Nova Lake, Diamond Rapids |
More APX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.