INVLPGB

if CPL > 0:
    fault(GP, 0)
a = low(rax, ASIZE)              # rAX: EAX with a 67 prefix
e = cpuid_leaf(0x80000008, 0)
nested = e[1] >> 21 & 1          # bit 5 allowed (EBX[21])
if a & 0xFC0 or a & 0x20 and not nested:
    fault(GP, 0)                 # reserved bits set
if edx >> 28:
    fault(GP, 0)                 # EDX bits 31:28 reserved
g = edx & 0xFFFF                 # the ASID: 0 is the host's
pcid = edx >> 16 & 0xFFF
if pcid and not cr4 >> 17 & 1:
    fault(GP, 0)                 # PCIDs off (CR4.PCIDE)
if g and not efer >> 12 & 1:
    fault(GP, 0)                 # SVM off (EFER.SVME)
if g > cpuid_leaf(0x8000000A, 0)[1]:
    fault(GP, 0)                 # past the number of ASIDs
if ecx & 0xFFFF > e[3] & 0xFFFF:
    fault(GP, 0)                 # a count past the maximum
# rAX bits 3:0 say what a translation must match to be dropped: the
# address in bits 63:12 (bit 0), the PCID (1), the ASID (2), and
# whether global ones count (3); bit 4, the last level only; bit 5,
# nested translations too. ECX[15:0] more pages after the first,
# 4 KiB apart, or 2 MiB with ECX[31]. On every processor, which do
# it in their own time: TLBSYNC waits for them