INVPCID

INVPCID drops translations from this logical processor’s TLBs and paging-structure caches by process-context identifier (PCID), the 12-bit tag that CR3 carries while CR4.PCIDE is set, so that the TLB can hold the translations of several address spaces at once. INVLPG reaches only the current PCID; INVPCID names its own in a 16-byte descriptor in memory, with the PCID in bits 11:0, zeros in bits 63:12 and a linear address in bits 127:64. The register operand, 64 bits in 64-bit mode and 32 bits outside it, gives the type.

Four types#

• 0: one address under one PCID, global translations kept.
• 1: every translation of one PCID, global ones kept.
• 2: every translation of every PCID, global ones too.
• 3: every translation of every PCID except global ones.

Each drops every entry of a page held as several smaller entries, and types 0, 1 and 3 may drop more than they name. A type above 3, a set bit in 63:12 or, for type 0, a non-canonical address raises #GP(0). With CR4.PCIDE clear, the processor caches PCID 0 alone: types 0 and 1 then need PCID 0 or raise #GP(0), and types 2 and 3 reach only PCID 0.

Where the vendors differ#

AMD documents the same encoding, 66 0F 38 82, the same types and the same CPUID bit, leaf 7, EBX bit 10. Its manual makes INVPCID serializing; Intel’s list of serializing instructions does not name it. AMD’s makes it raise #UD in real mode, where Intel’s lets it run, and in virtual-8086 mode, where Intel’s gives #GP(0). Under VMX, a guest gets #UD unless its hypervisor sets the “enable INVPCID” control.

In Linux#

Linux 7.3 names the four types in arch/x86/include/asm/invpcid.h. With page-table isolation, a process has a kernel PCID and a user PCID, and arch/x86/mm/tlb.c follows INVLPG with a type 0 for the user one; it flushes global pages with type 2 rather than two writes to CR4.

Running it#

INVPCID runs only at CPL 0. The Zen 5 behind this site’s recorded cases reports it in CPUID, and raised #GP in both cases, at CPL 3, with types 0 and 3. AMD’s Zen 5 guide lists INVPCID as microcoded, and says that support for it varies by model. GNU as 2.44 assembles it, but GCC 14 has neither an intrinsic nor an option for it; Clang 23 provides _invpcid(type, descriptor) with -minvpcid and zero-extends the 32-bit type into RAX.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0:
    fault(GP, 0)
t = kind.read()                  # 64 bits; 32 outside 64-bit mode
d = desc.read()                  # 128 bits
if t > 3:
    fault(GP, 0)
if d >> 12 & 0xFFFFFFFFFFFFF:
    fault(GP, 0)                 # bits 63:12 must be 0
pcid = d & 0xFFF                 # bits 11:0
a = d >> 64                      # bits 127:64, for type 0
if t < 2 and pcid and not cr4 >> 17 & 1:
    fault(GP, 0)                 # without PCIDs, PCID 0 alone
if t == 0 and not canonical(a):
    fault(GP, 0)
# type 0 drops the translations of address a under the PCID, but
# global ones; 1 all of the PCID's but global ones; 2 every one, of
# every PCID, global ones too; 3 every one but global ones. Each may
# drop more

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INVPCID

Attributes

What else XED records about the forms. How to read.

All forms

privileged: CPL 0 only; may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to INVPCID, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More APX instructions

• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI
• MOVRS
• MUL
• MULX
• NEG
• NOT
• OR
• PDEP
• PEXT
• POP2

All 88 APX instructions