x86-64.net

Instruction

INVPCID

Invalidates TLB entries and paging-structure caches for one address, one process-context identifier or all of them, as the type in a register selects.

Extensions
Forms
3 (2 Legacy, 1 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of INVPCID that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
INVPCID r64, m128 64-bit mode only INVPCID_GPR64_MEMdq66 0F 38 82 /rINVPCID
INVPCID r32, m128 not in 64-bit mode INVPCID_GPR32_MEMdq66 0F 38 82 /rINVPCID
INVPCID r64, m128 INVPCID_GPR64i64_MEMi128_APXEVEX.LLZ.F3.MAP4.WIG F2 /rAPX_F + INVPCID

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to INVPCID, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_invpcid void _invpcid(unsigned int __type, void *__descriptor)

INVPCID r64, m128 Legacy -minvpcid

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
INVPCID

INVPCID
CPUID.(EAX=07H,ECX=0):EBX[10] INVPCID

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest
APX_F_INVPCID

APX_F + INVPCID
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):EBX[10] INVPCID

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.