Jcc

A conditional jump almost always follows a CMP or TEST, and which mnemonic to use depends on whether the values compared are signed. After CMP a, b:

“Below” and “above” are the unsigned words, “less” and “greater” the signed ones. After TEST x, x, JZ means x is zero and JS that it is negative. The same four-bit condition code, whose lowest bit inverts the test, selects the condition in SETcc, CMOVcc and APX’s CCMPscc and CFCMOVcc.

Each condition has two encodings: 70+cc with an 8-bit displacement (2 bytes, for targets up to 128 bytes away) and 0F 80+cc with a 32-bit one (6 bytes). As for JMP and CALL, Intel’s manual fixes the operand size of near branches at 64 bits in 64-bit mode. AMD’s lets a 66 prefix make a Jcc 16 bits: a 2-byte displacement in the 0F 80+cc form and RIP cut to 16 bits, so those bytes have different lengths on the two.

Performance, by the vendors’ optimization manuals:

• Fusion. A CMP or TEST (and some arithmetic) directly followed by a Jcc is decoded as one operation. On Intel’s cores since Haswell, TEST and AND fuse with every condition, and CMP, ADD and SUB with all but the overflow, sign and parity ones, never when the first instruction has both a memory operand and an immediate. On Zen 5, CMP, TEST, SUB, ADD, INC, DEC, OR, AND and XOR fuse.
• Hints. The 3E prefix is a “taken” hint. From Intel’s Redwood Cove cores on, the processor uses it for a branch it has no history of; the 2E “not taken” hint is ignored.
• Unpredictable branches. Intel’s optimization manual suggests CMOVcc or SETcc in their place, but not for branches that predict well.

JRCXZ and LOOP are the jumps that test RCX rather than the flags.

In the optimization guide

What the optimization guide says about Jcc, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Front end

• Macro-fusion: Macro-fusion turns an instruction that sets the flags and the conditional branch right after it into one operation, which takes one slot in decode, rename and retirement.
• Macro-fusion: Intel’s cores since Sandy Bridge (Skylake) fuse test and and with any conditional branch; cmp, add and sub with branches on the equal, unsigned and signed comparisons, but not on the sign, parity or overflow flag alone; and inc and dec only with branches on equality and the signed comparisons.
• Macro-fusion: AMD’s Zen 3 to Zen 5 fuse more: cmp, test, add, sub, and, or, xor, inc and dec with any conditional branch, except that on Zen 3 and Zen 4 inc and dec do not fuse with a branch that reads the carry flag, which Intel’s cores do not fuse either (Zen 5, Zen 4, Zen 3). sources differ
• Code alignment and padding: On the Skylake family with the microcode update for its JCC erratum (Skylake), 32-byte boundaries matter for every jump: one that crosses such a boundary or ends on it is no longer cached and runs from the decoders.

Branches

• Direction and target: A conditional branch the predictor knows nothing about is predicted not taken. sources differ
• Direction and target: Prefixes 2Eh and 3Eh before a conditional jump once served as static hints, on the Pentium 4.
• Direction and target: LLVM 23.1.2 emits the taken hint only for Granite Rapids (-mtune=graniterapids), only with the hidden option -enable-branch-hint, and only on jumps that its branch probabilities put above 50%.

Bulldozer to Excavator

• Branches: A cmp or test directly followed by a conditional branch fuses into one op, unless the compare uses a RIP-relative address or has a displacement as well as an immediate; no other instruction fuses. sources differ

Golden Cove and Raptor Cove

• Branches: A conditional branch the predictor holds no history for is predicted not taken, so the rarely run branches that are usually taken cost a misprediction.

Ice Lake to Rocket Lake

• Front end: A cmp, add, sub, inc or dec fuses with a following jump on zero, carry or an unsigned or signed comparison, and test or and with any conditional jump; or, xor, adc, sbb, shifts and js, jo and jp never fuse.

Redwood Cove

• Branches: A conditional jump with a 3Eh prefix is a taken hint: when the predictor holds nothing on the branch, the decoder turns its default not-taken guess into taken and fetches from the target.
• Branches: The hint applies to Jcc only, not to jrcxz or loop.
• Branches: Hints pay on branches that run rarely and are mostly taken, where the predictor has likely forgotten them, as in programs with more branches than the predictor holds; on a hot branch it only makes the code longer.
• Branches: Redwood Cove’s performance events find the branches that a taken hint would help.

Silvermont to Goldmont Plus

• Front end: Back-to-back branches cost Silvermont and Goldmont 3 cycles in the decoders.

Skylake to Cooper Lake

• Front end: test and and fuse with any following conditional jump; cmp, add and sub with the jumps on equality and on the unsigned and signed comparisons, but not with js, jp or jo and their inverses; inc and dec only with those on equality and the signed comparisons.
• The JCC erratum: Under rare conditions a jump that crosses a 64-byte line could make these cores misbehave (erratum SKX102).

Zen and Zen+

• Integer execution: Only a cmp or test directly followed by a conditional branch fuses into one macro-op, and not when it has a displacement together with an immediate, or an address relative to RIP; no other arithmetic or logic instruction fuses.

Zen 2

• Integer execution: Only a cmp or test followed by a conditional branch fuses into one macro-op, not one with a displacement together with an immediate or an address relative to RIP; the arithmetic and logic instructions that fuse on Zen 3 do not.

Zen 3

• Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, unless it carries a displacement together with an immediate, addresses relative to RIP or makes the pair longer than 15 bytes; inc and dec do not fuse with a branch on the carry flag, and jrcxz never fuses.

Zen 4

• Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, unless it carries a displacement together with an immediate, addresses relative to RIP or makes the pair longer than 15 bytes; inc and dec do not fuse with a branch on the carry flag.

Zen 5

• Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, within limits on the sizes of its displacement and immediate.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

w = OSIZE                        # the size of the target
n = 0
if OSIZE == 16:                  # a 66 prefix
    if INTEL:
        w = 64                   # ignored: SDM
    else:
        if rel.bits == 32:
            n = 2                # a rel16, 2 bytes shorter than XED
                                 # decodes: APM, Zen 5
if cond(CC):                     # the flags from before the instruction
    t = low(rip - n + signed(rel), w)
    if not canonical(t):
        fault(GP, 0)
    rip = t
else:
    rip = rip - n                # on to the next instruction

Operands

Flags

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• DIV
• ENTER
• IDIV
• IMUL
• IN
• INC
• INS
• INT
• INT1
• INT3
• INTO
• IRET
• JCXZ
• JECXZ
• JMP
• JRCXZ
• LDS
• LEA
• LEAVE
• LES
• LFS
• LGS
• LODS
• LOOP
• LOOPE
• LOOPNE
• LSS
• MOV
• MOVS
• MOVSX
• MOVSXD
• MOVZX

All 109 General-purpose instructions