JCXZ instruction (General-purpose)

JCXZ jumps to a short relative target, -128 to +127 bytes from the next instruction, if CX is zero, and changes neither CX nor any flag. It is the 16-bit-address member of the opcode E3, beside JECXZ and JRCXZ: the address size picks the register. In 16-bit code E3 alone is JCXZ; in 32-bit code it takes a 67 prefix, 67 E3. In 64-bit mode the 67 prefix gives a 32-bit address, so JCXZ cannot be encoded there, and both manuals say so. JRCXZ’s page explains the instruction’s use as a guard in front of a LOOP, which in 16-bit code counts in CX.

Address size and operand size

The prefix changes only what is tested, not how the target is computed. The target is the address of the next instruction plus the sign-extended displacement, truncated to the operand size: to 16 bits in 16-bit code, so that a jump wraps within the 64 KB segment, and to 32 bits in 32-bit code, where 67 E3 tests CX but jumps with a full EIP. A 66 prefix in 16-bit code makes the operand size 32, so the same E3 tests CX and keeps all of EIP. A target beyond the code segment’s limit raises #GP(0).

Tools

GNU as 2.44 and Clang 23 encode jcxz as E3 in .code16 and as 67 E3 in .code32, and both reject it in 64-bit code, Clang 23 with “instruction requires: Not 64-bit mode”. The probe that records this site’s Zen 5 cases runs in 64-bit mode, so JCXZ has no case; JECXZ’s page shows the 67 E3 form there.

Forms

Every encoding of JCXZ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`JCXZ rel8` not in 64-bit mode JCXZ_RELBRb	`67 E3 cb`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if cx == 0:                      # CX: JCXZ is a 67 prefix outside 64-bit
    rip = low(rip + sext(rel), OSIZE)   # mode, where it does not exist

Not run on a processor: JCXZ does not exist in 64-bit mode, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`JCXZ rel8` not in 64-bit mode
`rel8`	explicit	read
`CX`	implicit	read
`IP`	implicit	read, write

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I386` General-purpose	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Address size and operand size#

Tools#