JECXZ instruction (General-purpose)

JECXZ jumps to a short relative target, -128 to +127 bytes from the next instruction, if ECX is zero, and changes neither ECX nor any flag. It shares the opcode E3 with JCXZ and JRCXZ; the address size picks the register. In 32-bit code, E3 alone is JECXZ. In 64-bit mode it takes a 67 prefix, which makes JRCXZ test ECX instead of RCX, and in 16-bit code too, where E3 alone is JCXZ. JRCXZ’s page explains why the instruction exists, as a guard in front of a LOOP, and why compilers leave it out.

In 64-bit mode

The 67 prefix changes only the register that is tested: the target is still RIP plus the sign-extended displacement, computed in 64 bits. On Zen 5, JECXZ with RCX = 2^32 jumped, since ECX was zero, and with ECX = FFFFFFFFH it did not; JRCXZ does not jump for 2^32. A count kept in a 32-bit register is the case where the two agree, since writing ECX clears bits 63:32.

After a repeated compare

Intel’s manual gives JECXZ a second use: after REPE or REPNE CMPS or SCAS, which stop when ECX reaches zero or when ZF changes, JECXZ tells which one ended the repeat. A zero ECX alone is not conclusive, though, since the last element may also have decided the compare; ZF says that.

Neither GCC 14 nor Clang 23 emits it in our builds, for 32-bit code at -O2 or -Os, even with -march=i386. AMD’s Zen 5 guide lists JECXZ as one macro-op on the branch unit.

Forms

Every encoding of JECXZ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`JECXZ rel8` JECXZ_RELBRb	`67 E3 cb`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`rel8`
Sandy Bridge	2 / 1p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	2 / 0.5p0156
Alder Lake, Sapphire Rapids	2 / 0.5p0 p1 p5 p6 p11
Lunar Lake	2 / 0.33p012345
Bonnell	4 / 2p01
Silvermont	1 / 1IEC1
Piledriver	1 / 1Branch EX1
Zen, Zen 2	1 / 0.5ALU0 ALU3
Zen 3, Zen 4	1 / 0.5ALU0 BRU1
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if ecx == 0:                     # ECX alone: bits 63:32 of RCX do not
    t = rip + sext(rel)          # count (a 67 prefix on JRCXZ)
    if not canonical(t):
        fault(GP, 0)
    rip = t

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`JECXZ rel8`
`rel8`	explicit	read
`ECX`	implicit	read
`RIP`	implicit	read, write

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I386` General-purpose	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

In 64-bit mode#

After a repeated compare#