x86-64.net

Instruction

JMPABS

APX jump to a 64-bit absolute address given as an immediate, encoded with a REX2 prefix as an 11-byte instruction.

Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Before APX, a jump to an arbitrary 64-bit address needed the target in a register or in memory, which makes it an indirect branch. JMPABS carries the target as a 64-bit immediate, so it is a direct jump that can reach anywhere in the address space. The encoding is the REX2 prefix with M0=0 and W=0, the opcode A1 and the eight-byte target: 11 bytes in all.

A non-canonical target raises #GP. The 66, 67, F0, F2 and F3 prefixes make it raise #UD, and segment overrides are ignored. Performance monitoring and last branch records treat it like any direct jump, but unlike other direct jumps, Intel Processor Trace reports its target with a TIP packet.

Forms

Every encoding of JMPABS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
JMPABS imm64 JMPABS_ABSBRu64_APXREX2.W0 A1 ioAPX_F

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.