Instruction
JMPABS
APX jump to a 64-bit absolute address given as an immediate, encoded with a REX2 prefix as an 11-byte instruction.
- Extensions
- Forms
- 1 (1 Legacy)
- Data
- Intel XED v2026.08.23
Before APX, a jump to an arbitrary 64-bit address needed the target in a register or in memory, which makes it an indirect branch. JMPABS carries the target as a 64-bit immediate, so it is a direct jump that can reach anywhere in the address space. The encoding is the REX2 prefix with M0=0 and W=0, the opcode A1 and the eight-byte target: 11 bytes in all.
A non-canonical target raises #GP. The 66, 67, F0, F2 and F3 prefixes make it raise #UD, and segment overrides are ignored. Performance monitoring and last branch records treat it like any direct jump, but unlike other direct jumps, Intel Processor Trace reports its target with a TIP packet.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
JMPABS imm64
JMPABS_ABSBRu64_APX | REX2.W0 A1 io | APX_F |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
t = target.read() # the 64-bit address, as encoded
if not canonical(t):
fault(GP, 0)
rip = tNot run on a processor: none of these processors has APX.
Operands
| Operand | Kind | Action |
|---|---|---|
JMPABS imm64 | ||
imm64 | explicit | read |
RIP | implicit | write |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
APX-LEGACY-JMPABS
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
APX_F | APX_F | Nova Lake, Diamond Rapids |
More APX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 9.0 (355828-009, August 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.