JRCXZ instruction (General-purpose)

JRCXZ jumps to a short relative target, -128 to +127 bytes from the next instruction, if RCX is zero. It tests the register itself, not a flag, and changes neither RCX nor RFLAGS. The opcode E3 is the one that names JCXZ and JECXZ: the address size picks the register, so in 64-bit mode E3 alone is JRCXZ, and with a 67 prefix it is JECXZ, which tests ECX. JCXZ has no encoding in 64-bit mode.

All 64 bits count

Zen 5 did not jump for RCX = 2^32, whose low half is zero, nor for 2^63. JECXZ, given the same 2^32, did jump: it looks at ECX alone. A count passed in a 32-bit register reaches JRCXZ intact, since writing ECX clears bits 63:32.

Uses

There is only the 8-bit displacement: unlike a Jcc, it has no 0F form with 32 bits, so a far target needs test rcx, rcx and JZ instead. Its classic place is in front of a LOOP, whose decrement before the test would turn a count of 0 into 2^64 passes; LOOP’s page shows that edge. Not touching the flags also lets it test a count in the middle of code that carries CF from step to step, as an ADC chain does.

Neither GCC 14 nor Clang 23 emits it in our builds, at -O2 or at -Os: a loop that may run zero times starts with TEST and JE. AMD’s Zen 5 guide lists JRCXZ and JECXZ as one macro-op on the branch unit, where LOOP and its kin are microcoded.

In the optimization guide

What the optimization guide says about JRCXZ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 3

Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, unless it carries a displacement together with an immediate, addresses relative to RIP or makes the pair longer than 15 bytes; inc and dec do not fuse with a branch on the carry flag, and jrcxz never fuses.

Forms

Every encoding of JRCXZ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`JRCXZ rel8` 64-bit mode only JRCXZ_RELBRb	`E3 cb`	LM

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`rel8`
Sandy Bridge	2 / 1p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	2 / 0.5p0156
Alder Lake, Sapphire Rapids	2 / 0.5p0 p1 p5 p6 p11
Lunar Lake	2 / 0.33p012345
Bonnell	4 / 2p01
Silvermont	1 / 1IEC1
Piledriver	1 / 1Branch EX1
Zen, Zen 2	1 / 0.5ALU0 ALU3
Zen 3, Zen 4	1 / 0.5ALU0 BRU1
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if rcx == 0:
    t = rip + sext(rel)
    if not canonical(t):
        fault(GP, 0)
    rip = t

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`JRCXZ rel8` 64-bit mode only
`rel8`	explicit	read
`RCX`	implicit	read
`RIP`	implicit	read, write

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`LONGMODE` General-purpose System SYSCALL/SYSRET	LM `CPUID.80000001H:EDX[29]` LM	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

All 64 bits count#

Uses#