x86-64.net

Instruction

KADDB

Adds two 8-bit mask registers as unsigned integers.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KADDB adds the low 8 bits of two mask registers as integers and writes the 8-bit sum to a third, with bits 63:8 cleared. It is KADDW for eight-element masks, and that page explains what an addition does to a mask: m + m shifts it, and carries ripple up through runs of ones, which is how vector code adds numbers wider than an element. Like KADDW it needs AVX512DQ.

Recorded on Zen 5

The carry out of bit 7 is dropped and no flag is written; RFLAGS kept its value in all 11 cases.

  • Wrapping. FFh plus 1 gave 0, 80h plus 80h gave 0, and E2h plus 1Eh, 100h, gave 0 as well; 7Fh plus 1 gave 80h and FFh plus FFh FEh.
  • Only the low byte. A source of FFFFFFFFFFFFFF7Fh counted as 7Fh.
  • Twice a mask. kaddb k7, k7, k7 turned A9h into 52h, the same as a shift left by one with bit 7 lost.

In compiled code

The compilers part as for words. For m + n on two compare masks of eight doubles, used as the write mask of an add, Clang 23 at -O2 with -march=x86-64-v4 emits KADDB, the width of the mask, where for sixteen elements KADDW’s page found KADDD; GCC 14 moves both masks to general-purpose registers with KMOVB, adds there and moves the sum back. _kadd_mask8 gives KADDB in both.

AMD’s Zen 5 latency spreadsheet gives KADDB one cycle and two per cycle on pipes FP0 and FP3, as KADDW.

Forms

Every encoding of KADDB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KADDB k, k, k KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512VEX.L1.66.0F.W0 4A /rAVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, k
Skylake-SP, Ice Lake, Sapphire Rapids4 / 1p5
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.b[0] = k2.b[0] + k3.b[0]      # the carry out of bit 7 is lost
# bits 63:8 of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KADDB k, k, k
kexplicitwrite
kexplicitread
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KADDB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kadd_mask8 __mmask8 _kadd_mask8(__mmask8 __A, __mmask8 __B)

KADDB k, k, k VEX.L1 -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512DQ_KOPB

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-513 (KADDW/KADDB/KADDQ/KADDD)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.