x86-64.net

Instruction

KADDD

Adds two 32-bit mask registers as unsigned integers.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KADDD adds the low 32 bits of two mask registers as integers and writes the 32-bit sum to a third, with bits 63:32 cleared. It is KADDW for masks of 32 elements, such as those of word compares on ZMM registers or byte compares on YMM registers, and that page explains what an addition does to a mask. The carry out of bit 31 is lost and no flag is written. KADDD and KADDQ need AVX512BW; KADDB and KADDW come with AVX512DQ.

Recorded on Zen 5

RFLAGS kept its value in all 11 cases.

  • Wrapping. FFFFFFFFh plus 1 gave 0, and 80000000h plus 80000000h gave 0; 7FFFFFFFh plus 1 gave 80000000h.
  • Only the low half. 68108DF800000000h plus FFFFFFFF00000000h gave 0: the upper halves of the sources do not take part, and the destination’s upper half was cleared.
  • K0 is a value. kaddd k6, k7, k0 read K0 like any other mask register, FFFFFFFFh in its low half, and gave FFFFFFFEh. Only as a write mask does K0 mean “no mask”.

In compiled code

At -O2 with -march=x86-64-v4, for m + n on two __mmask32 word compare results used as a write mask, Clang 23 emits KADDD between the compares and the masked move. GCC 14 moves both masks to general-purpose registers with KMOVD, adds them with ADD and moves the sum back; it emits KADDD only for _kadd_mask32, which Clang compiles the same way. For m + m both use KSHIFTLD or, on a 64-bit mask, KSHIFTLQ.

AMD’s Zen 5 latency spreadsheet gives one macro-op with a latency of one cycle, two per cycle on pipes FP0 and FP3, as for KADDW.

Forms

Every encoding of KADDD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KADDD k, k, k KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512VEX.L1.66.0F.W1 4A /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, k
Skylake-SP, Ice Lake, Sapphire Rapids4 / 1p5
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.d[0] = k2.d[0] + k3.d[0]      # the carry out of bit 31 is lost
# bits 63:32 of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KADDD k, k, k
kexplicitwrite
kexplicitread
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KADDD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kadd_mask32 __mmask32 _kadd_mask32(__mmask32 __A, __mmask32 __B)

KADDD k, k, k VEX.L1 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512BW_KOPD

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-513 (KADDW/KADDB/KADDQ/KADDD)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.