x86-64.net

Instruction

KADDW

Adds two 16-bit mask registers as unsigned integers.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KADDW adds the low 16 bits of two mask registers as integers and writes the 16-bit sum to a third, with bits 63:16 cleared. It is the only arithmetic among the mask instructions; the others are logic, shifts, moves and tests. The carry out of bit 15 is lost and no flag is written, so an overflow leaves no trace: in the cases recorded on Zen 5, FFFFh plus 1 gave 0 and 7FFFh plus 1 gave 8000h, with RFLAGS unchanged. KADDW needs AVX512DQ, which also brings KADDB; KADDD and KADDQ come with AVX512BW.

What an addition does to a mask

Read as one bit per element, adding moves carries upward through runs of ones, which no single logic instruction does. Two cases are worth knowing:

  • m + m is m shifted left by one, and both GCC 14 and Clang 23 at -O2 compile it so, to KSHIFTLW.
  • Adding 1 to a mask clears its run of ones at the bottom and sets the first zero above it. More generally, (g « 1) + p, with g marking elements that produce a carry and p those that pass one on, yields after an XOR with p the elements that receive a carry. That is how vector code adds numbers wider than an element, such as integers of several quadwords: the carries ripple through all elements in one addition rather than one element per step.

In compiled code

Compilers rarely choose it. With -march=x86-64-v4, m + n on two __mmask16 compare results used as a write mask becomes KMOVW to general-purpose registers, an ADD and a KMOVW back in GCC 14, and KADDD in Clang 23, whose upper bits do not matter for 16 elements; with AVX512DQ but no AVX512BW, Clang goes through general-purpose registers too. Only the intrinsic _kadd_mask16 gives KADDW in both.

AMD’s Zen 5 guide lists KADDW, like KADDQ, as one macro-op with a latency of one cycle.

Forms

Every encoding of KADDW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KADDW k, k, k KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512VEX.L1.NP.0F.W0 4A /rAVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, k
Skylake-SP, Ice Lake, Sapphire Rapids4 / 1p5
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.w[0] = k2.w[0] + k3.w[0]      # the carry out of bit 15 is lost
# bits 63:16 of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KADDW k, k, k
kexplicitwrite
kexplicitread
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KADDW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kadd_mask16 __mmask16 _kadd_mask16(__mmask16 __A, __mmask16 __B)

KADDW k, k, k VEX.L1 -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512DQ_KOPW

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-513 (KADDW/KADDB/KADDQ/KADDD)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.