x86-64.net

Instruction

KANDNB

Computes the bitwise AND of the inverted first 8-bit mask with the second.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KANDNB inverts the low 8 bits of its first source, ANDs them with the low 8 bits of the second and writes the result to a third mask register, clearing every bit above bit 7: kandnb k1, k2, k3 gives K1 = ~K2 & K3 in the low byte. It is the AVX512DQ form of KANDNW, whose page explains the operand order, for masks with one bit per quadword of a ZMM register; KANDND and KANDNQ are the 32- and 64-bit forms.

Recorded on Zen 5

  • Only the low byte counts. A first source of AAh against 4C17BF272A35BEFFh gave 55h; a first source of all ones gave 0 whatever the second held.
  • The upper bits are cleared. kandnb k3, k1, k3 with K3 all ones and 00h in the low byte of K1 left FFh: bits 63:8 became 0.
  • One register twice gives 0, in kandnb k5, k6, k6 and kandnb k7, k7, k7 alike.

In compiled code

At -O2 with -march=x86-64-v4, GCC 14 compiles _kandn_mask8(_mm512_cmpeq_epi64_mask(a, b), _mm512_cmpeq_epi64_mask(a, c)) to two VPCMPQ with predicate 0 and a KANDNB, also when the result then masks a VMOVDQA64. Clang 23 needs no mask logic: it compares for “not equal” first and for equality under that mask, which leaves the AND in the second result, and GCC does the same for the floating-point ~m1 & m2 with VCMPPD. _kandn_mask8 of two arguments is two KMOVB, KANDNB and a KMOVB back in GCC, and a NOT and an AND on AL in Clang.

AMD’s Zen 5 latency spreadsheet gives KANDNB one macro-op, one cycle, two per cycle on pipes FP0 and FP3, as KANDNW.

Forms

Every encoding of KANDNB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KANDNB k, k, k KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512VEX.L1.66.0F.W0 42 /rAVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, k
Skylake-SP, Ice Lake, Sapphire Rapids1 / 1p0
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.b[0] = ~k2.b[0] & k3.b[0]     # the bits of k3 where k2 has 0
# bits 63:8 of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KANDNB k, k, k
kexplicitwrite
kexplicitread
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KANDNB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kandn_mask8 __mmask8 _kandn_mask8(__mmask8 __A, __mmask8 __B)

KANDNB k, k, k VEX.L1 -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512DQ_KOPB

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-515 (KANDNW/KANDNB/KANDNQ/KANDND)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.