x86-64.net

Instruction

KANDNW

Computes the bitwise AND of the inverted first 16-bit mask with the second.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KANDNW inverts its first source, ANDs the result with the second and writes the low 16 bits to a third mask register, clearing bits 63:16: kandnw k1, k2, k3 gives K1 = ~K2 & K3, the bits of K3 that K2 does not have. The inverted operand is the first source, as in ANDN for general-purpose registers and PANDN and ANDNPS for vectors, so “remove the elements of m from n” is kandnw kd, m, n. It belongs to AVX-512F with KANDW, which describes the word-sized mask logic as a family; KANDNB needs AVX512DQ, and KANDND and KANDNQ AVX512BW.

The cases recorded on Zen 5 cover the edges: with the same register named twice, as in kandnw k5, k6, k6, the result is 0 whatever K6 holds, and the bits above 15 of the sources never reach the result, so a K2 of FFFFFFFFFFFF5555h against AAAAh gave AAAAh. KANDNW with a register of all ones as its second source is a 16-bit NOT, which KNOTW also does.

In compiled code

Compilers rarely need it. The AND of one compare with the negation of another becomes an inverted predicate under a mask: with GCC 14 and Clang 23 at -O2 and -mavx512f, m1 & ~m2 for two float compares x < y and x < z compiled to two VCMPPS, one of them with the “not less than” predicate and the other run under its mask, and the integer version to VPCMPD with an inverted predicate in the same way. A mask kept across loop iterations, todo &= ~cmp, stayed in general-purpose registers in both: a KMOVW out, then NOT and AND in GCC, or an inverted compare and an AND in Clang.

KANDNW itself comes from intrinsics. GCC compiles _kandn_mask16(a, b) and _mm512_kandn(a, b) on two __mmask16 arguments to two KMOVW, a KANDNW and a KMOVW back to EAX. Clang’s headers have no _kandn_mask16, and Clang turns _mm512_kandn into NOT and AND on general-purpose registers, as it does for KANDW.

The instruction table of AMD’s Zen 5 guide lists KANDNW, like KANDW, as one macro-op with a latency of one cycle.

Forms

Every encoding of KANDNW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KANDNW k, k, k KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512VEX.L1.NP.0F.W0 42 /rAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, k
Skylake-SP, Ice Lake, Sapphire Rapids1 / 1p0
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.w[0] = ~k2.w[0] & k3.w[0]     # the bits of k3 where k2 has 0
# bits 63:16 of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KANDNW k, k, k
kexplicitwrite
kexplicitread
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KANDNW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm512_kandn __mmask16 _mm512_kandn(__mmask16 __A, __mmask16 __B)

KANDNW k, k, k VEX.L1 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512F_KOPW

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-515 (KANDNW/KANDNB/KANDNQ/KANDND)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.