KANDW instruction (AVX10.1)

KANDW ANDs the low 16 bits of two mask registers into a third and clears bits 63:16 of the result. Bits above 15 of the sources play no part: the cases recorded on Zen 5 give sources whose upper bits are all ones and still get 16-bit results. Since the destination is a separate operand, one mask can be combined with several others without being copied first.

KANDW belongs to AVX-512F, with the other word-sized mask logic: KORW, KXORW, KXNORW, KNOTW and KANDNW, which ANDs the inverted first source with the second. The byte form, KANDB, needs AVX512DQ, and KANDD and KANDQ need AVX512BW.

Two conditions at once

Intel’s optimization manual uses KANDW to join two compares into the mask of a loop body that runs where x > 0 && (x & 3) == 3 (Section 17.2.4). Compilers mostly find something shorter. With GCC 14 and Clang 23 at -O2 and -mavx512f, the AND of two compare masks used as a write mask became:

in both compilers, for compares of floats, the second compare run under the first one’s mask, as in vcmpps k1{k1}, zmm0, zmm2, 17: a masked compare writes 0 for every element its mask excludes, which is the AND;
in Clang, for a > b && a > c on signed doublewords, one VPMAXSD and one compare, since a is greater than both exactly when it is greater than their maximum.

KANDW itself shows up when the operands are masks already: GCC compiles _mm512_kand(a, b) on two __mmask16 arguments to two KMOVW instructions, KANDW and a KMOVW back to EAX, while Clang ANDs the arguments in general-purpose registers.

The instruction table of AMD’s Zen 5 guide lists KANDW, like KORW, KXORW, KNOTW and KANDNW, as one macro-op with a latency of one cycle.

In the optimization guide

What the optimization guide says about KANDW, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

Masks and masked memory access: Mask logic such as KANDW combines conditions, while moving a mask from a general register costs two macro-ops on Zen 4 and Zen 5.

Forms

Every encoding of KANDW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`KANDW k, k, k` KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512	`VEX.L1.NP.0F.W0 41 /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`k, k, k`
Skylake-SP, Ice Lake, Sapphire Rapids	1 / 1p0
Zen 4	1 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.w[0] = k2.w[0] & k3.w[0]
# bits 63:16 of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`KANDW k, k, k`
`k`	explicit	write
`k`	explicit	read
`k`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KANDW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm512_kand` `__mmask16 _mm512_kand(__mmask16 __A, __mmask16 __B)`	`KANDW k, k, k` VEX.L1 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512F_KOPW` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX512F_KOPW

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Two conditions at once#