KMOVD instruction (AVX10.1, APX)

KMOVD moves the low 32 bits of a mask register: to or from another mask register, four bytes of memory or a 32-bit general-purpose register. Thirty-two bits are one per word of a ZMM register or one per byte of a YMM register, the masks of AVX512BW, which KMOVD needs. KMOVW describes the family and KMOVQ the full 64-bit move. A mask register destination gets bits 63:32 cleared, and a general-purpose one is zero-extended: on Zen 5, kmovd k1, k2 with K2 all ones left K1 = FFFFFFFFh, and kmovd r9d, k0 took only the low half of K0.

AVX2’s PMOVMSKB, done with a mask

The 32-bit mask is what VPMOVMSKB gives for a YMM register, and code compiled for AVX-512 gets it through KMOVD instead. With -march=x86-64-v4, Clang 23 at -O2 turns even the AVX2 intrinsics _mm256_movemask_epi8(_mm256_cmpeq_epi8(a, b)) into a VPCMPEQB that writes K0 and kmovd eax, k0; GCC 14 keeps VPCMPEQB into a vector and VPMOVMSKB. Written with _mm256_cmpeq_epi8_mask, both use KMOVD, and TZCNT of the result finds the first equal byte. For words in a ZMM register:

returning _mm512_cmpeq_epi16_mask(a, b) as a __mmask32, or counting its bits with POPCNT, goes through kmovd eax, k0 in both;
storing such a mask is kmovd dword ptr [rdi], k0 in both, while a stored mask is loaded with KMOVD from memory by Clang and with a MOV and kmovd k1, eax by GCC;
the mask for the last n words of a buffer is made with BZHI of all ones and moved in with kmovd k1, eax, ready for a zero-masked VMOVDQU16.

The conversion intrinsics _cvtu32_mask32 and _cvtmask32_u32 are no instructions of their own: a __mmask32 passed between functions lives in a general-purpose register, and the compilers move it into a mask register only where an instruction needs it there.

AMD’s Zen 5 guide lists kmovd k, r32 as two macro-ops with a latency of two cycles and kmovd r32, k as one with a latency of one, as for KMOVQ. APX adds EVEX encodings whose general-purpose forms reach R16 to R31; Zen 5 has no APX, so they were not run.

Forms

Every encoding of KMOVD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`KMOVD k, k` KMOVD_MASKmskw_MASKu32_AVX512	`VEX.LZ.66.0F.W1 90 /r`	AVX10.1 or AVX512BW
`KMOVD k, m32` KMOVD_MASKmskw_MEMu32_AVX512	`VEX.LZ.66.0F.W1 90 /r`	AVX10.1 or AVX512BW
`KMOVD m32, k` KMOVD_MEMu32_MASKmskw_AVX512	`VEX.LZ.66.0F.W1 91 /r`	AVX10.1 or AVX512BW
`KMOVD k, r32` KMOVD_MASKmskw_GPR32u32_AVX512	`VEX.LZ.F2.0F.W0 92 /r`	AVX10.1 or AVX512BW
`KMOVD r32, k` KMOVD_GPR32u32_MASKmskw_AVX512	`VEX.LZ.F2.0F.W0 93 /r`	AVX10.1 or AVX512BW
`KMOVD r32, k` KMOVD_GPR32u32_MASKmskw_APX	`EVEX.LLZ.F2.0F.W0 93 /r`	AVX10.1 + APX_F or APX_F + AVX512BW
`KMOVD m32, k` KMOVD_MEMu32_MASKmskw_APX	`EVEX.LLZ.66.0F.W1 91 /r`	AVX10.1 + APX_F or APX_F + AVX512BW
`KMOVD k, k` KMOVD_MASKmskw_MASKu32_APX	`EVEX.LLZ.66.0F.W1 90 /r`	AVX10.1 + APX_F or APX_F + AVX512BW
`KMOVD k, m32` KMOVD_MASKmskw_MEMu32_APX	`EVEX.LLZ.66.0F.W1 90 /r`	AVX10.1 + APX_F or APX_F + AVX512BW
`KMOVD k, r32` KMOVD_MASKmskw_GPR32u32_APX	`EVEX.LLZ.F2.0F.W0 92 /r`	AVX10.1 + APX_F or APX_F + AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`k, k`	`k, m32`	`m32, k`	`k, r32`	`r32, k`
Skylake-SP	1 / 1p0	7 / 1p0156	1 / 1p2347	1 / 1p5	3 / 1p0
Ice Lake	1 / 1p0	7 / 1p0156	1 / 0.5p4789	1 / 1p5	3 / 1p0
Sapphire Rapids	1 / 1p0	7 / 1p5	12 / 0.5p4789	3 / 1p5	3 / 1p0
Zen 4	1 / 0.5FP2 FP3	5 / 0.33AGU0 AGU1 AGU2 LSU Load	1 / 0.5FP45	1 / 0.5¹FP45	1 / 0.5FP2 FP3

Zen 4 model: AMD's spreadsheets give reciprocal throughput 1 for Zen 4 and Zen 5 (AMD 57647, row 336; AMD 58455, row 977).

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = low(src, 32)                 # a mask register: the bits above 31
                                 # are ignored
dest.write(v)                    # a mask register: bits 63:32
                                 # cleared, as they are in the 64-bit
                                 # register of r32; m32: four bytes
# the APX forms (EVEX) move the same way, and reach R16 to R31

Run on AMD Zen 5 (EPYC 9645): 22 cases. The APX forms were not run: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`KMOVD k, k/m32`
`k`	explicit	write
`k/m32`	explicit	read
`KMOVD r/m32, k`
`r/m32`	explicit	write
`k`	explicit	read
`KMOVD k, r32`
`k`	explicit	write
`r32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

KMOVD k, k/m32 KMOVD m32, k: AVX512-K21
KMOVD k, r32 KMOVD r32, k: AVX512-K20
EVEX forms: APX-EVEX-KMOV

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KMOVD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_load_mask32` `__mmask32 _load_mask32(__mmask32 *__A)`	`KMOVD k, m32` VEX.LZ -mavx512bw
`_store_mask32` `void _store_mask32(__mmask32 *__A, __mmask32 __B)`	`KMOVD m32, k` VEX.LZ -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512BW_KOPD` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
`APX_F_KOPD` APX	AVX10.1 + APX_F `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or APX_F + AVX512BW `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW	Nova Lake, Diamond Rapids

AVX512BW_KOPD

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

APX_F_KOPD

AVX10.1 + APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

APX_F + AVX512BW
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Nova Lake, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

More APX instructions

All 88 APX instructions

AVX2’s PMOVMSKB, done with a mask#