x86-64.net

Instruction

KMOVQ

Moves a 64-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers.

Extensions
Forms
10 (5 VEX, 5 EVEX)
Data
Intel XED v2026.08.23

KMOVQ moves all 64 bits of a mask register: to or from another mask register, memory, or a 64-bit general-purpose register. Sixty-four bits are one per byte of a ZMM register, so KMOVQ belongs with the byte compares of AVX512BW, which it needs, as KMOVD does for the 32-bit masks of word elements. KMOVW describes the family and the AVX-512F form; this page is the one that carries a whole 64-byte comparison.

A mask in a general-purpose register

The common pattern scans bytes: compare 64 of them at once, then work on the mask with the scalar bit instructions. GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile it as follows.

  • A loop that looks for a byte, testing _mm512_cmpeq_epi8_mask(chunk, key), leaves with KORTESTQ of the mask with itself, then moves the mask to RAX with kmovq rax, k0 and finds the first match with TZCNT.
  • Counting the equal bytes is KMOVQ and POPCNT.
  • The other way, a mask built in a general-purpose register becomes a write mask with kmovq k1, rax. For the last n bytes of a buffer, both compilers make the mask with BZHI of all ones and load under it with VMOVDQU8 and {z}; the bytes the mask leaves out cannot fault, even past the end of a page.

The forms with a general-purpose register share their opcode bytes with KMOVD’s and differ only in VEX.W, which is 1 for KMOVQ; as they name a 64-bit register, they exist only in 64-bit mode. In the cases recorded on Zen 5, every form moved the 64 bits unchanged, upper half included.

AMD’s Zen 5 guide lists kmovq k, r64 as two macro-ops with a latency of two cycles and kmovq r64, k as one with a latency of one, so moving a mask out to scalar code is the cheaper direction.

APX adds EVEX encodings of the five forms, whose general-purpose ones reach R16 to R31 as well. Zen 5 has no APX, so they were not run.

Forms

Every encoding of KMOVQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KMOVQ k, k KMOVQ_MASKmskw_MASKu64_AVX512VEX.LZ.NP.0F.W1 90 /rAVX10.1 or AVX512BW
KMOVQ k, m64 KMOVQ_MASKmskw_MEMu64_AVX512VEX.LZ.NP.0F.W1 90 /rAVX10.1 or AVX512BW
KMOVQ m64, k KMOVQ_MEMu64_MASKmskw_AVX512VEX.LZ.NP.0F.W1 91 /rAVX10.1 or AVX512BW
KMOVQ k, r64 64-bit mode only KMOVQ_MASKmskw_GPR64u64_AVX512VEX.LZ.F2.0F.W1 92 /rAVX10.1 or AVX512BW
KMOVQ r64, k 64-bit mode only KMOVQ_GPR64u64_MASKmskw_AVX512VEX.LZ.F2.0F.W1 93 /rAVX10.1 or AVX512BW
KMOVQ k, k KMOVQ_MASKmskw_MASKu64_APXEVEX.LLZ.NP.0F.W1 90 /rAVX10.1 + APX_F or APX_F + AVX512BW
KMOVQ k, m64 KMOVQ_MASKmskw_MEMu64_APXEVEX.LLZ.NP.0F.W1 90 /rAVX10.1 + APX_F or APX_F + AVX512BW
KMOVQ k, r64 KMOVQ_MASKmskw_GPR64u64_APXEVEX.LLZ.F2.0F.W1 92 /rAVX10.1 + APX_F or APX_F + AVX512BW
KMOVQ r64, k KMOVQ_GPR64u64_MASKmskw_APXEVEX.LLZ.F2.0F.W1 93 /rAVX10.1 + APX_F or APX_F + AVX512BW
KMOVQ m64, k KMOVQ_MEMu64_MASKmskw_APXEVEX.LLZ.NP.0F.W1 91 /rAVX10.1 + APX_F or APX_F + AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, kk, m64m64, kk, r64r64, k
Skylake-SP1 / 1p07 / 1p01561 / 1p23471 / 1p53 / 1p0
Ice Lake1 / 1p07 / 1p01561 / 0.5p47891 / 1p53 / 1p0
Sapphire Rapids1 / 1p07 / 1p512 / 0.5p47891 / 1p53 / 1p0
Zen 41 / 0.5FP2 FP35 / 0.33AGU0 AGU1 AGU2 LSU Load1 / 0.5FP451 / 0.5FP451 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(src)                  # all 64 bits, between mask
                                 # registers, r64 and m64
# the APX forms (EVEX) move the same way, and reach R16 to R31

Run on AMD Zen 5 (EPYC 9645): 22 cases. The APX forms were not run: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KMOVQ k, k/m64
kexplicitwrite
k/m64explicitread
KMOVQ k, r64 64-bit mode only
kexplicitwrite
r64explicitread
KMOVQ r/m64, k
r/m64explicitwrite
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Forms only in 64-bit mode
AVX512-K20
EVEX forms
APX-EVEX-KMOV
Other forms
AVX512-K21

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KMOVQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_load_mask64 __mmask64 _load_mask64(__mmask64 *__A)

KMOVQ k, m64 VEX.LZ -mavx512bw

_store_mask64 void _store_mask64(__mmask64 *__A, __mmask64 __B)

KMOVQ m64, k VEX.LZ -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512BW_KOPQ

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
APX_F_KOPQ

AVX10.1 + APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

APX_F + AVX512BW
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Nova Lake, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 9.0 (355828-009, August 2026)
  7. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-517 (KMOVW/KMOVB/KMOVQ/KMOVD)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.