KMOVW

KMOVW moves 16 bits into or out of one of the eight AVX-512 mask registers, K0 to K7: from another mask register, from memory or from a 32-bit general-purpose register, and back to those. Sixteen bits are one bit per element of a ZMM register of doublewords or singles, and KMOVW is the only mask move of AVX-512F; KMOVB needs AVX512DQ, and KMOVD and KMOVQ need AVX512BW. As the page’s pseudocode says, a mask register destination gets bits 63:16 cleared, and a general-purpose destination is written whole, the 32-bit register zero-extended to 64 bits. K0 is an ordinary operand here; only as a write mask does its number mean “no mask” (Intel’s optimization guide, Section 17.2).

Where compiled code uses it#

The masks themselves come from compares, such as VPCMPD, which write a mask register directly; KMOVW is how a mask meets ordinary integer code. With GCC 14 and Clang 23 at -O2 and AVX-512F:

• Returning _mm512_cmpgt_epi32_mask(a, b) as a __mmask16 moves it to EAX with kmovw eax, k0, and a mask built in a general-purpose register, such as the one BZHI makes for the last n elements of a buffer, comes back with kmovw k1, eax.
• Counting the selected elements is KMOVW and POPCNT; testing whether any is selected needs no move at all: KORTESTW of the mask with itself sets ZF when it is zero.
• A __mmask16 in memory is stored with the memory form; Clang also loads it with one, while GCC loads it with MOVZX and moves it over.
• The AND of two compares needs no KANDW either: both compilers run the second compare under the first’s mask.

When AVX512BW is also enabled, as with -march=x86-64-v4, Clang 23 uses KMOVD for most moves between mask and general-purpose registers, which gives the same 16 bits since a compare of doublewords clears the mask bits above 15; GCC 14 keeps KMOVW.

APX adds EVEX encodings that reach the general-purpose registers R16 to R31. Zen 5 has no APX, so the recorded cases cover the VEX forms only.

In the optimization guide

What the optimization guide says about KMOVW, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Masks and masked memory access: Mask logic such as KANDW combines conditions, while moving a mask from a general register costs two macro-ops on Zen 4 and Zen 5.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = low(src, 16)                 # a mask register or r32: the bits
                                 # above 15 are ignored
dest.write(v)                    # a mask register: bits 63:16
                                 # cleared; r32: bits 63:16 of its
                                 # 64-bit register cleared; m16: two
                                 # bytes
# the APX forms (EVEX) move the same way, and reach R16 to R31

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

KMOVW k, k/m16 KMOVW m16, k KMOVW k, r32

AVX512-K21

KMOVW r32, k

AVX512-K20

EVEX forms

APX-EVEX-KMOV

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KMOVW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• KADDB
• KADDD
• KADDQ
• KADDW
• KANDB
• KANDD
• KANDNB
• KANDND
• KANDNQ
• KANDNW
• KANDQ
• KANDW
• KMOVB
• KMOVD
• KMOVQ
• KNOTB
• KNOTD
• KNOTQ
• KNOTW
• KORB
• KORD
• KORQ
• KORTESTB
• KORTESTD
• KORTESTQ
• KORTESTW
• KORW
• KSHIFTLB
• KSHIFTLD
• KSHIFTLQ
• KSHIFTLW
• KSHIFTRB
• KSHIFTRD
• KSHIFTRQ
• KSHIFTRW
• KTESTB
• KTESTD
• KTESTQ
• KTESTW
• KUNPCKBW

All 686 AVX10.1 instructions

More APX instructions

• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI
• MOVRS
• MUL
• MULX
• NEG
• NOT
• OR
• PDEP
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP

All 88 APX instructions