x86-64.net

Instruction

KMOVW

Moves a 16-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers.

Extensions
Forms
10 (5 VEX, 5 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of KMOVW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KMOVW k, k KMOVW_MASKmskw_MASKu16_AVX512VEX.LZ.NP.0F.W0 90 /rAVX10.1 or AVX512F
KMOVW k, m16 KMOVW_MASKmskw_MEMu16_AVX512VEX.LZ.NP.0F.W0 90 /rAVX10.1 or AVX512F
KMOVW m16, k KMOVW_MEMu16_MASKmskw_AVX512VEX.LZ.NP.0F.W0 91 /rAVX10.1 or AVX512F
KMOVW k, r32 KMOVW_MASKmskw_GPR32u32_AVX512VEX.LZ.NP.0F.W0 92 /rAVX10.1 or AVX512F
KMOVW r32, k KMOVW_GPR32u32_MASKmskw_AVX512VEX.LZ.NP.0F.W0 93 /rAVX10.1 or AVX512F
KMOVW k, k KMOVW_MASKmskw_MASKu16_APXEVEX.LLZ.NP.0F.W0 90 /rAVX10.1 + APX_F or APX_F + AVX512F
KMOVW k, m16 KMOVW_MASKmskw_MEMu16_APXEVEX.LLZ.NP.0F.W0 90 /rAVX10.1 + APX_F or APX_F + AVX512F
KMOVW k, r32 KMOVW_MASKmskw_GPR32u32_APXEVEX.LLZ.NP.0F.W0 92 /rAVX10.1 + APX_F or APX_F + AVX512F
KMOVW r32, k KMOVW_GPR32u32_MASKmskw_APXEVEX.LLZ.NP.0F.W0 93 /rAVX10.1 + APX_F or APX_F + AVX512F
KMOVW m16, k KMOVW_MEMu16_MASKmskw_APXEVEX.LLZ.NP.0F.W0 91 /rAVX10.1 + APX_F or APX_F + AVX512F

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512F_KOPW

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
APX_F_KOPW

AVX10.1 + APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

APX_F + AVX512F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Nova Lake, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
  3. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.