x86-64.net

Instruction

KNOTB

Inverts every bit of an 8-bit mask.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KNOTB writes the inverse of the low 8 bits of one mask register to another and clears bits 63:8 of the destination. It is KNOTW for masks of eight elements, the doubles or quadwords of a ZMM register, and that page explains why compilers mostly invert the compare instead. KNOTB needs AVX512DQ, like the other byte-sized mask logic such as KANDB and KORB.

Recorded on Zen 5

  • Only the low byte. FFFFFFFFFFFFFF01h gave FEh, and all ones gave 0: bits 63:8 of the source did not show in the result.
  • The upper bits are cleared. Every one of the nine results fit in a byte, among them FFh from 04C26206A4043B00h and 7Fh from C31058A1E7942B80h.
  • One register, and K0. knotb k7, k7 turned CEE3DBE7E9FE7CDAh into 25h, and knotb k4, k0 read K0, 3Bh, to give C4h.

In compiled code

With GCC 14 and Clang 23 at -O2 and -march=x86-64-v4, ~ of a compare of doubles used as a write mask becomes the inverted predicate, “not less than” for “less than”, with no KNOTB. GCC keeps KNOTB where one mask serves both arms of an if: for a function that multiplies where a < b and adds elsewhere, written with _knot_mask8, it compares once with VCMPPD, runs VMULPD under the mask and VADDPD under its KNOTB. Clang multiplies every element and adds under the inverted predicate. With only -mavx512f, which lacks KNOTB, GCC inverts the mask of the same function, written with ~, by KNOTW: the bits it sets above bit 7 fall outside the eight elements. _knot_mask8 of an argument is KMOVB, KNOTB and KMOVB in GCC, and NOT on AL in Clang.

AMD’s Zen 5 latency spreadsheet gives KNOTB one cycle and two per cycle on pipes FP0 and FP3, as KNOTW.

Forms

Every encoding of KNOTB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KNOTB k, k KNOTB_MASKmskw_MASKmskw_AVX512VEX.LZ.66.0F.W0 44 /rAVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k
Skylake-SP, Ice Lake, Sapphire Rapids1 / 1p0
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.b[0] = ~k2.b[0]
# bits 63:8 of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KNOTB k, k
kexplicitwrite
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KNOTB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_knot_mask8 __mmask8 _knot_mask8(__mmask8 __M)

KNOTB k, k VEX.LZ -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512DQ_KOPB

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-519 (KNOTW/KNOTB/KNOTQ/KNOTD)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.