x86-64.net

Instruction

KNOTW

Inverts every bit of a 16-bit mask.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KNOTW writes the inverse of the low 16 bits of one mask register to another and clears bits 63:16 of the destination. Inverting a mask turns the elements a condition selected into those it left out, the else branch of a vectorized if. KNOTW is part of AVX-512F; KNOTB needs AVX512DQ, and KNOTD and KNOTQ AVX512BW.

Usually the compare is inverted instead

A compare already chooses its condition with its predicate, so a compiler that needs only the inverse mask asks for it directly. With GCC 14 and Clang 23 at -O2 and -mavx512f, the mask ~_mm512_cmpgt_epi32_mask(a, b) compiled to a single compare for less-or-equal. For floats the inverse of “less than” is “not less than”, which holds for NaNs too, unlike “greater or equal”. Both compilers kept that meaning: GCC with predicate 21 (NLT_UQ) and Clang with predicate 5 (NLT_US), which differ only in that a quiet NaN sets the invalid flag with the second, whereas the program’s _CMP_LT_OQ sets it for none.

Both branches

When the same mask serves both arms of an if, one compare and one KNOTW give the two masks. Intel’s optimization manual shows that pair, VPCMPGTD and KNOTW, in front of two masked shifts that handle the two cases in one register (Section 17.2.3, Example 17-6), and measures the version that computes both results and blends them as faster. For a function that multiplies where a < b and adds elsewhere, written with _mm512_knot, GCC kept the KNOTW; Clang computed the products for every element and then overwrote them with sums under the inverted compare, which needs only the one mask.

KANDNW inverts its first operand on the way into an AND, so ~a & b needs no separate KNOTW, and KXNORW of a register with itself gives all ones. The instruction table of AMD’s Zen 5 guide lists KNOTW as one macro-op with a latency of one cycle.

Forms

Every encoding of KNOTW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KNOTW k, k KNOTW_MASKmskw_MASKmskw_AVX512VEX.LZ.NP.0F.W0 44 /rAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k
Skylake-SP, Ice Lake, Sapphire Rapids1 / 1p0
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.w[0] = ~k2.w[0]
# bits 63:16 of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KNOTW k, k
kexplicitwrite
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KNOTW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm512_knot __mmask16 _mm512_knot(__mmask16 __M)

KNOTW k, k VEX.LZ -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512F_KOPW

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-519 (KNOTW/KNOTB/KNOTQ/KNOTD)
  7. Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.