x86-64.net

Instruction

KORQ

Computes the bitwise OR of two 64-bit masks.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KORQ ORs all 64 bits of two mask registers into a third. It is the AVX512BW form of KORW, which describes the mask logic and when compilers need it, for masks of one bit per byte of a ZMM register, as the byte compares such as VPCMPUB and VPCMPEQB produce them. KANDQ is its AND partner. In the cases recorded on Zen 5 every bit took part: 5555555555555555h and AAAAAAAAAAAAAAAAh gave all ones, two masks of random bits gave their exact OR, and korq k0, k4, k5 wrote K0, which mask logic treats like any other mask register.

Two characters in 64 bytes

Searching a buffer for either of two bytes, such as a comma or a newline, takes two byte compares and their OR. With GCC 14 and Clang 23 at -O2 and -march=x86-64-v4, and the intrinsics _mm512_cmpeq_epi8_mask for both:

  • When the OR becomes a write mask, for a masked blend of the matching bytes, both compilers emit KORQ.
  • When it decides a branch, Clang tests both masks with KORTESTQ and computes the KORQ only after a match, to find its position with TZCNT; GCC moves both masks to general-purpose registers with KMOVQ and ORs them there.
  • For two adjacent characters, 'a' and 'b', Clang needs no OR at all: it subtracts 'a' from every byte and makes one unsigned compare with 2, as VPCMPUB’s range tests do.

The intrinsic _kor_mask64 on two __mmask64 arguments is two KMOVQs, KORQ and a KMOVQ back to RAX in GCC, and an OR of RDI and RSI in Clang.

AMD’s latency spreadsheet for Zen 5 lists KORQ as it lists KORW and KORD: one macro-op with a latency of one cycle.

Forms

Every encoding of KORQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KORQ k, k, k KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512VEX.L1.NP.0F.W1 45 /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, k
Skylake-SP, Ice Lake, Sapphire Rapids1 / 1p0
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.q[0] = k2.q[0] | k3.q[0]

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KORQ k, k, k
kexplicitwrite
kexplicitread
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KORQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kor_mask64 __mmask64 _kor_mask64(__mmask64 __A, __mmask64 __B)

KORQ k, k, k VEX.L1 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512BW_KOPQ

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-522 (KORW/KORB/KORQ/KORD)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.