KORTESTB instruction (AVX10.1)

KORTESTB is KORTESTW for eight-element masks: it ORs the low 8 bits of two mask registers, sets ZF when the result is zero and CF when it is FFh, clears OF, SF, AF and PF, and writes no mask. Eight elements are what a ZMM register of doubles or quadwords holds, or a YMM register of doublewords, so KORTESTB is the branch test after their compares. Like KTESTB, it needs AVX512DQ (or AVX10); KORTESTW is part of AVX-512F.

Only the low byte counts

Bits 63:8 of both masks play no part, as Zen 5 recorded: two masks whose low bytes were zero set ZF although many of their upper bits were set, and a K0 ending in FFh set CF with K6 zero. 55h and AAh, which share no bit, also set CF together, since their OR is FFh. A compare of eight elements writes zeros above bit 7, so KORTESTW would give the same ZF there; the difference shows with masks loaded from elsewhere, and in CF, which KORTESTW sets only for FFFFh.

In compiled code

GCC 14 and Clang 23 at -O2 with -mavx512f -mavx512dq compile a search loop over doubles, _mm512_cmp_pd_mask against a key and a branch on the mask, to VCMPPD, kortestb k0, k0 and a JE or JNE. With -mavx512f alone both move the mask to a general-purpose register with KMOVW and test its low byte instead.

The two-mask form appears for (m1 | m2) != 0, where Clang emits kortestb k0, k1 after the two compares, while GCC moves both masks out with KMOVB and ORs them in general-purpose registers.

Neither compiler used CF for the all-ones test. For eight quadwords all equal, mask == 0xFF, Clang instead compares the same registers as sixteen doublewords for inequality and tests that mask for zero with KORTESTW; GCC compares the moved-out byte with -1. The intrinsics _kortestz_mask8_u8 and _kortestc_mask8_u8 give KORTESTB with SETE or SETC in GCC, while Clang computes them with OR and CMP in general-purpose registers.

KORTESTD and KORTESTQ cover the 32- and 64-element masks of words and bytes and need AVX512BW. The instruction table of AMD’s Zen 5 guide lists KORTESTB, like KORTESTW, as two macro-ops.

Forms

Every encoding of KORTESTB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`KORTESTB k, k` KORTESTB_MASKmskw_MASKmskw_AVX512	`VEX.LZ.66.0F.W0 98 /r`	AVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`k, k`
Skylake-SP, Ice Lake, Sapphire Rapids	3 / 1p0
Zen 4	1 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = low(k1 | k2, 8)              # bits 63:8 of both are ignored
zf = v == 0
cf = v == 0xFF                   # all eight bits set
of = sf = af = pf = 0

Run on AMD Zen 5 (EPYC 9645): 12 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`KORTESTB k, k`
`k`	explicit	read
`k`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	0	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KORTESTB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_kortestc_mask8_u8` `unsigned char _kortestc_mask8_u8(__mmask8 __A, __mmask8 __B)`	`KORTESTB k, k` VEX.LZ -mavx512dq
`_kortestz_mask8_u8` `unsigned char _kortestz_mask8_u8(__mmask8 __A, __mmask8 __B)`	`KORTESTB k, k` VEX.LZ -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512DQ_KOPB` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

AVX512DQ_KOPB

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Only the low byte counts#

In compiled code#