x86-64.net

Instruction

KORTESTD

ORs two 32-bit masks and sets ZF if the result is all zeros and CF if it is all ones.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KORTESTD ORs the low 32 bits of two mask registers and sets ZF when the result is zero and CF when it is FFFFFFFFh, clearing OF, SF, AF and PF; it writes no mask. It is KORTESTW for the 32 elements of a ZMM register of words or a YMM register of bytes, and that page and KORTESTB’s explain how branches use it. It needs AVX512BW.

Recorded on Zen 5

The 12 recorded cases set the flags from bits 31:0 alone:

  • 0D725FDF00000000h and 3830701700000000h, zero in their low halves, set ZF.
  • A K0 of F99B3057FFFFFFFFh with K6 zero set CF, as did 55555555h with AAAAAAAAh, which share no bit.
  • 80000000h with 80000001h set neither, and every case cleared OF, SF, AF and PF, even where they had been set.

In compiled code

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile a search over short elements, _mm512_cmpeq_epi16_mask against a key and a branch on the mask, to VPCMPEQW with the array as memory operand, kortestd k0, k0 and a JE or JNE. As for the other widths, the two-mask form appears for (m1 | m2) != 0 in Clang only, GCC ORs the masks in general-purpose registers, and neither uses CF for mask == 0xFFFFFFFF: Clang compares as doublewords for inequality and tests with KORTESTW, GCC compares with -1 in EAX. _kortestz_mask32_u8 and _kortestc_mask32_u8 give KORTESTD with SETE or SETC in GCC, OR and CMP in Clang.

AMD’s Zen 5 latency spreadsheet lists KORTESTD as two macro-ops on pipes FP0 or FP3 and FP4 or FP5, two per cycle, as KORTESTW.

Forms

Every encoding of KORTESTD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KORTESTD k, k KORTESTD_MASKmskw_MASKmskw_AVX512VEX.LZ.66.0F.W1 98 /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k
Skylake-SP, Ice Lake, Sapphire Rapids3 / 1p0
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = low(k1 | k2, 32)             # bits 63:32 of both are ignored
zf = v == 0
cf = v == 0xFFFFFFFF             # all 32 bits set
of = sf = af = pf = 0

Run on AMD Zen 5 (EPYC 9645): 12 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KORTESTD k, k
kexplicitread
kexplicitread
RFLAGSimplicitwrite

Flags

M modified, 0 cleared; blank: not affected. How to read.
OFSFZFAFPFCF
All forms
00M00M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KORTESTD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kortestc_mask32_u8 unsigned char _kortestc_mask32_u8(__mmask32 __A, __mmask32 __B)

KORTESTD k, k VEX.LZ -mavx512bw

_kortestz_mask32_u8 unsigned char _kortestz_mask32_u8(__mmask32 __A, __mmask32 __B)

KORTESTD k, k VEX.LZ -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512BW_KOPD

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-520 (KORTESTW/KORTESTB/KORTESTQ/KORTESTD)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.