KORTESTW

KORTESTW ORs the low 16 bits of two mask registers and keeps only the answer in the flags: ZF is set when the OR is zero, CF when it is all ones (FFFFh), and OF, SF, AF and PF are cleared. No mask register is written. It is how a branch reads a mask, since AVX-512’s compares write mask registers rather than vectors or flags.

Leaving a loop#

The common use names one mask twice: kortestw k0, k0 sets ZF when no element was selected. GCC 14 and Clang 23 at -O2 and -mavx512f compile a search loop that tests _mm512_cmpeq_epi32_mask(v, key) to a VPCMPEQD with the array as its memory operand, KORTESTW of the result with itself, and a JE or JNE; Intel’s optimization manual leaves its conflict loop for a histogram the same way (Example 17-24). Two different masks fold the OR in: for (m1 | m2) != 0 Clang emits kortestw k0, k1, where GCC moves both masks to general-purpose registers with KMOVW and ORs them there.

The all-ones test#

CF answers “every element selected?”, but neither compiler used it for mask == 0xFFFF. Clang inverted the compare (VPCMPNEQD) and tested the new mask for zero with KORTESTW; GCC moved the mask to EAX and compared it with -1. Only the intrinsic _kortestc_mask16_u8 gets KORTESTW and SETC from GCC; Clang turns it into OR and CMP in general-purpose registers.

Its relatives#

KTESTW sets ZF from the AND of its operands and CF from the AND with one of them inverted, as PTEST does for vectors; it needs AVX512DQ, while KORTESTW is part of AVX-512F. KORTESTB needs AVX512DQ, and KORTESTD and KORTESTQ AVX512BW, for the masks of byte and word elements. The instruction table of AMD’s Zen 5 guide lists KORTESTW as two macro-ops.

In the optimization guide

What the optimization guide says about KORTESTW, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Masks and masked memory access: Mask logic such as KANDW combines conditions, while moving a mask from a general register costs two macro-ops on Zen 4 and Zen 5.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = low(k1 | k2, 16)             # bits 63:16 of both are ignored
zf = v == 0
cf = v == 0xFFFF                 # all 16 bits set
of = sf = af = pf = 0

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KORTESTW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• KANDNB
• KANDND
• KANDNQ
• KANDNW
• KANDQ
• KANDW
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• KNOTB
• KNOTD
• KNOTQ
• KNOTW
• KORB
• KORD
• KORQ
• KORTESTB
• KORTESTD
• KORTESTQ
• KORW
• KSHIFTLB
• KSHIFTLD
• KSHIFTLQ
• KSHIFTLW
• KSHIFTRB
• KSHIFTRD
• KSHIFTRQ
• KSHIFTRW
• KTESTB
• KTESTD
• KTESTQ
• KTESTW
• KUNPCKBW
• KUNPCKDQ
• KUNPCKWD
• KXNORB
• KXNORD
• KXNORQ
• KXNORW

All 686 AVX10.1 instructions