x86-64.net

Instruction

KORW

Computes the bitwise OR of two 16-bit masks.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KORW ORs the low 16 bits of two mask registers into a third and clears bits 63:16 of the result; the sources’ upper bits are ignored. As a write mask, the result selects every element that either condition selected, which is how an if (p || q) is vectorized when the two conditions come from separate compares. It is part of AVX-512F; KORB needs AVX512DQ, and KORD and KORQ AVX512BW.

In compiled code

Unlike an AND, an OR cannot be folded into a masked compare, since masking only ever clears bits. With GCC 14 and Clang 23 at -O2 and -mavx512f, the OR of two compares of floats, used as the mask of an add, is two VCMPPS instructions and a KORW in both compilers. For a > b || a > c on signed doublewords Clang needs no KORW: a is greater than one of them exactly when it is greater than their minimum, so it emits VPMINSD and a single compare, while GCC keeps the two compares and the KORW.

When the OR only decides a branch, it is not written to a register at all: KORTESTW ORs its two operands for the flags, and Clang compiles (m1 | m2) != 0 to kortestw k0, k1. GCC moves both masks to general-purpose registers with KMOVW and ORs them there instead.

The intrinsic _mm512_kor on two __mmask16 function arguments shows the compilers’ general difference with mask values in general-purpose registers: GCC moves them into mask registers for KORW and back, Clang uses an ordinary OR.

The instruction table of AMD’s Zen 5 guide lists KORW as one macro-op with a latency of one cycle, the same as KANDW and the other mask logic instructions.

Forms

Every encoding of KORW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KORW k, k, k KORW_MASKmskw_MASKmskw_MASKmskw_AVX512VEX.L1.NP.0F.W0 45 /rAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, k
Skylake-SP, Ice Lake, Sapphire Rapids1 / 1p0
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.w[0] = k2.w[0] | k3.w[0]
# bits 63:16 of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KORW k, k, k
kexplicitwrite
kexplicitread
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KORW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm512_kor __mmask16 _mm512_kor(__mmask16 __A, __mmask16 __B)

KORW k, k, k VEX.L1 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512F_KOPW

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-522 (KORW/KORB/KORQ/KORD)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.