x86-64.net

Instruction

KSHIFTLQ

Shifts a 64-bit mask left by an immediate count, filling with zeros.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KSHIFTLQ shifts all 64 bits of a mask register left by an immediate count, fills with zeros from the right, and writes the result to another mask register. It is the 64-bit form of KSHIFTLW, whose page explains why a mask is shifted and that the count is taken whole from the 8-bit immediate, and of KSHIFTLD; it needs AVX512BW, for masks with one bit per byte of a ZMM register. KSHIFTRQ shifts the other way.

Recorded on Zen 5

  • Counts of 64 and up give zero. Counts of 64, 65, 79, 128 and 255 all gave 0, also from a register of all ones, so the count is not reduced modulo 64 as SHL reduces its own.
  • Bit 63 is lost. A shift by one turned 8000000000000001h into 2, and a shift by 63 of 5555555555555555h left only 8000000000000000h.
  • The lower half to the upper. kshiftlq k5, k5, 0x20 turned DB13DF08077B52D0h into 077B52D000000000h.

In compiled code

A shift by one lines each byte’s bit up with the byte after it, which finds a pair of bytes: (m1 << 1) & m2, with m1 the bytes equal to 'x' and m2 those equal to 'y', marks every 'y' that follows an 'x'. With GCC 14 and Clang 23 at -O2 and -march=x86-64-v4, used as a write mask, it is kshiftlq k1, k0, 1 in both, and the second compare runs under the shifted mask, which leaves the AND in its result. Returned as a uint64_t, GCC keeps the same three instructions and moves the result out with KMOVQ, while Clang moves both compare masks to general-purpose registers and shifts with ADD. _kshiftli_mask64(m, 32) of a byte compare is KSHIFTLQ in both, and KXORQ’s page shows it in m ^ (m << 1).

AMD’s Zen 5 latency spreadsheet gives KSHIFTLQ one cycle and two per cycle on pipes FP0 and FP3, as KSHIFTLW.

Forms

Every encoding of KSHIFTLQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KSHIFTLQ k, k, imm8 KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512VEX.LZ.66.0F3A.W1 33 /r ibAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, imm8
Skylake-SP, Ice Lake, Sapphire Rapids4 / 1p5
Zen 41 / 0.5FP1 FP2

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = k2.read()
n = imm8.read()                  # 0 to 255, not masked
k1.write(low(v << n, 64))        # bits past bit 63 are lost

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KSHIFTLQ k, k, imm8
kexplicitwrite
kexplicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KSHIFTLQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kshiftli_mask64 __mmask64 _kshiftli_mask64(__mmask64 A, const unsigned int I)

KSHIFTLQ k, k, imm8 VEX.LZ -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512BW_KOPQ

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-523 (KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.