x86-64.net

Instruction

KSHIFTLW

Shifts a 16-bit mask left by an immediate count, filling with zeros.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KSHIFTLW shifts the low 16 bits of a mask register left by an immediate count, fills with zeros from the right, and writes the 16-bit result to another mask register with bits 63:16 cleared. Bits shifted past bit 15 are lost; they do not reach bit 16, and the source’s own bits above 15 never enter. Moving a mask’s bits up by n lines them up with the elements n places higher, the way a vector shift or VALIGND moves the data.

The count is not masked

Unlike SHL, which uses only the low 5 or 6 bits of its count, KSHIFTLW takes all 8 bits of the immediate: any count of 16 or more gives zero. The cases recorded on Zen 5 show this for counts 16, 17, 63, 64, 128, 200 and 255, all with zero results, and the page’s pseudocode says the same.

In compiled code

A shift alone on a __mmask16 does not need KSHIFTLW: C promotes the mask to int, and GCC 14 and Clang 23 at -O2 return _mm512_cmpeq_epi32_mask(a, b) << 1 with KMOVW to EAX and an ADD of EAX to itself. KSHIFTLW appears when the result stays a mask, either through the intrinsic _kshiftli_mask16 or in an expression whose result is used as one: both compilers compile m ^ (m << 1), used as a write mask, to KSHIFTLW and KXORW, which marks the elements where the condition changes from the one below. Intel’s optimization manual uses the same pair in its top-k search (Example 8-14).

Its relatives

KSHIFTRW shifts right, with zeros from the left; GCC and Clang compile _kshiftri_mask16(m, 8) before a masked add to it, to apply the upper half of a mask to the lower eight elements. The byte form, KSHIFTLB, needs AVX512DQ, and KSHIFTLD and KSHIFTLQ AVX512BW. The instruction table of AMD’s Zen 5 guide lists KSHIFTLW as one macro-op with a latency of one cycle.

Forms

Every encoding of KSHIFTLW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KSHIFTLW k, k, imm8 KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512VEX.LZ.66.0F3A.W1 32 /r ibAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, imm8
Skylake-SP, Ice Lake, Sapphire Rapids4 / 1p5
Zen 41 / 0.5FP1 FP2

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = low(k2, 16)                  # bits 63:16 of k2 are ignored
n = imm8.read()                  # 0 to 255, not masked
k1.write(low(v << n, 16))        # bits past bit 15 are lost; bits
                                 # 63:16 of k1 cleared

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KSHIFTLW k, k, imm8
kexplicitwrite
kexplicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KSHIFTLW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kshiftli_mask16 __mmask16 _kshiftli_mask16(__mmask16 A, const unsigned int I)

KSHIFTLW k, k, imm8 VEX.LZ -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512F_KOPW

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-523 (KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD)
  7. Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.