x86-64.net

Instruction

KSHIFTRB

Shifts an 8-bit mask right by an immediate count, filling with zeros.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KSHIFTRB shifts the low 8 bits of a mask register right by an immediate count, fills with zeros from the left, and writes the 8-bit result to another mask register with bits 63:8 cleared. It is KSHIFTRW for masks of eight elements, the doubles or quadwords of a ZMM register; that page shows that the source is read only as wide as the instruction and the count taken whole. It needs AVX512DQ, like KSHIFTLB, which shifts the other way.

Recorded on Zen 5

  • Only 8 bits come in. By one, 49A928B95BE37781h gave 40h, not C0h: bit 8 of the source, set, did not move into bit 7. By four, 86918D0C7955CF54h gave 05h.
  • The count is not masked. Counts of 8, 9, 63, 64, 117, 128 and 255 gave 0, even from all ones, where SHR would have masked 64 and 128 to 0 and left its operand unchanged.
  • Upper bits are cleared. A shift by 0 of all ones gave FFh.

In compiled code

With GCC 14 and Clang 23 at -O2 and -march=x86-64-v4, the mask of a VCMPPD of eight doubles shifted right and used as the write mask of an add stays in the mask registers in both: m >> 1 gives KSHIFTRB, and m ^ (m >> 1), which marks the elements where the condition changes from the one above, KSHIFTRB and KXORB; for the 16-bit form KSHIFTRW’s page finds Clang going through EAX instead. _kshiftri_mask8(m, 4), which puts the upper four elements’ bits over the lower four, is KSHIFTRB in both. Returned as an integer, the shifted mask is a KMOVB (GCC) or KMOVD (Clang) out and SHR on AL.

AMD’s Zen 5 latency spreadsheet gives KSHIFTRB one cycle and two per cycle on pipes FP0 and FP3, as KSHIFTRW.

Forms

Every encoding of KSHIFTRB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KSHIFTRB k, k, imm8 KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512VEX.LZ.66.0F3A.W0 30 /r ibAVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, imm8
Skylake-SP, Ice Lake, Sapphire Rapids4 / 1p5
Zen 41 / 0.5FP1 FP2

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = low(k2, 8)                   # bits 63:8 of k2 are ignored: none
                                 # shifts in at bit 7
n = imm8.read()                  # 0 to 255, not masked
k1.write(v >> n)                 # bits 63:8 cleared

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KSHIFTRB k, k, imm8
kexplicitwrite
kexplicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KSHIFTRB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kshiftri_mask8 __mmask8 _kshiftri_mask8(__mmask8 A, const unsigned int I)

KSHIFTRB k, k, imm8 VEX.LZ -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512DQ_KOPB

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-525 (KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.