x86-64.net

Instruction

KSHIFTRD

Shifts a 32-bit mask right by an immediate count, filling with zeros.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KSHIFTRD shifts the low 32 bits of a mask register right by an immediate count, fills with zeros from the left, and writes the result to another mask register with bits 63:32 cleared. It is the 32-bit form of KSHIFTRW, whose page shows that the source is read only as wide as the instruction and that the count is taken whole from the 8-bit immediate; it needs AVX512BW, like KSHIFTRQ.

Recorded on Zen 5

  • Bit 32 does not come in. With 48D2C63180000001h as source, a shift by one gave 40000000h: bit 31 moved to bit 30 and the set bit 32 stayed out.
  • Counts of 32 and up give zero. The 11 cases include counts of 0, 1, 16, 31, 32, 33, 63, 64, 128, 189 and 255; from 32 on every result was 0, even for an all-ones source, so the count is not reduced modulo 32 or 64 as SHR reduces its own. A count of 0 copied FFFFFFFFh out of an all-ones register.
  • Half a mask down. kshiftrd k5, k5, 0x10 turned E76FB8B849807D2Eh into 4980h, the upper word of the low half.

In compiled code

With GCC 14 and Clang 23 at -O2 and -march=x86-64-v4, _kshiftri_mask32(m, 16) of a word compare is KSHIFTRD, which puts the upper 16 elements’ bits over the lower 16. Unlike the 16-bit case on KSHIFTRW’s page, m ^ (m >> 1) used as a write mask stays in the mask registers in both compilers, KSHIFTRD and KXORD.

AMD’s Zen 5 latency spreadsheet gives KSHIFTRD one cycle and two per cycle on pipes FP0 and FP3, as KSHIFTRW.

Forms

Every encoding of KSHIFTRD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KSHIFTRD k, k, imm8 KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512VEX.LZ.66.0F3A.W0 31 /r ibAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, imm8
Skylake-SP, Ice Lake, Sapphire Rapids4 / 1p5
Zen 41 / 0.5FP1 FP2

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = low(k2, 32)                  # bits 63:32 of k2 are ignored: none
                                 # shifts in at bit 31
n = imm8.read()                  # 0 to 255, not masked
k1.write(v >> n)                 # bits 63:32 cleared

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KSHIFTRD k, k, imm8
kexplicitwrite
kexplicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KSHIFTRD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kshiftri_mask32 __mmask32 _kshiftri_mask32(__mmask32 A, const unsigned int I)

KSHIFTRD k, k, imm8 VEX.LZ -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512BW_KOPD

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-525 (KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.