x86-64.net

Instruction

KSHIFTRQ

Shifts a 64-bit mask right by an immediate count, filling with zeros.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KSHIFTRQ shifts all 64 bits of a mask register right by an immediate count, fills with zeros from the left, and writes the result to another mask register. It is the 64-bit form of KSHIFTRW, whose page shows that the count is taken whole from the 8-bit immediate, and of KSHIFTRD; it needs AVX512BW, for masks with one bit per byte of a ZMM register.

Recorded on Zen 5

  • Counts of 64 and up give zero. The nine cases include counts of 0, 1, 26, 32, 63, 64, 65, 128 and 255; from 64 on every result was 0, even for an all-ones source, so the count is not reduced modulo 64 as SHR reduces its own.
  • Bit 63 moves down. A shift by one turned 8000000000000001h into 4000000000000000h, and a shift by 26 of all ones left 3FFFFFFFFFh, 38 bits.
  • The upper half to the lower. kshiftrq k5, k5, 0x20 turned 9D4E5C1D87E3FE1Bh into 9D4E5C1Dh.

In compiled code

With GCC 14 and Clang 23 at -O2 and -march=x86-64-v4, _kshiftri_mask64(m, 32) of a byte compare is KSHIFTRQ, which puts the upper 32 elements’ bits over the lower 32. Where the result goes to a general-purpose register anyway, as for mask >> 3 returned as a uint64_t, both move the mask out with KMOVQ and shift with SHR. When the shifted mask serves as a write mask, as in m ^ (m >> 1), which marks where a run of matching bytes starts or ends, it stays in the mask registers in both compilers: KSHIFTRQ by 1 and KXORQ, then a zero-masked VMOVDQU8.

AMD’s Zen 5 latency spreadsheet gives KSHIFTRQ one cycle and two per cycle on pipes FP0 and FP3, as KSHIFTRW.

Forms

Every encoding of KSHIFTRQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KSHIFTRQ k, k, imm8 KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512VEX.LZ.66.0F3A.W1 31 /r ibAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, imm8
Skylake-SP, Ice Lake, Sapphire Rapids4 / 1p5
Zen 41 / 0.5FP1 FP2

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = k2.read()
n = imm8.read()                  # 0 to 255, not masked
k1.write(v >> n)                 # zeros shift in at bit 63

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KSHIFTRQ k, k, imm8
kexplicitwrite
kexplicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KSHIFTRQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kshiftri_mask64 __mmask64 _kshiftri_mask64(__mmask64 A, const unsigned int I)

KSHIFTRQ k, k, imm8 VEX.LZ -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512BW_KOPQ

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-525 (KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.