x86-64.net

Instruction

KSHIFTRW

Shifts a 16-bit mask right by an immediate count, filling with zeros.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KSHIFTRW shifts the low 16 bits of a mask register right by an immediate count, fills with zeros from the left, and writes the result to another mask register with bits 63:16 cleared. Its mirror image, KSHIFTLW, describes what the two share: a count taken whole from the 8-bit immediate, so that 16 and more give zero, not masked as SHR masks its count.

Only 16 bits come in

The source is read as a 16-bit value: bits 16 and up of the source register never shift down into bit 15. The cases recorded on Zen 5 show it with a source whose bits 16, 15 and 0 were set and whose bits 14:1 were clear, 8001h in its low word: shifted right by one it gave 4000h, not C000h, and with a count of 17 it gave zero. A mask of all ones shifted by 0 gave FFFFh. A shift of the full 64-bit register needs KSHIFTRQ, which AVX512BW adds with KSHIFTRD; the byte form KSHIFTRB needs AVX512DQ.

Moving a mask to other elements

Shifting a mask right by n lines bit i + n up with element i. The intrinsic _kshiftri_mask16(m, 8) puts the upper half of a mask over the lower eight elements, and GCC 14 and Clang 23 at -O2 compile it to KSHIFTRW, after a KMOVW or KMOVD when the mask arrives in a general-purpose register.

Written in C, the shift is on an int, since C promotes __mmask16, and there the compilers part. For m >> 1 used as a write mask, and for m ^ (m >> 1), which marks the elements where a condition changes from the one above, GCC 14 with -march=x86-64-v4 stays in the mask registers with KSHIFTRW and KXORW. Clang 23 moves the mask to EAX with KMOVW, shifts and XORs there, and moves it back. When the shifted mask is returned as an integer, both use SHR in a general-purpose register.

AMD’s Zen 5 guide lists KSHIFTRW as one macro-op with a latency of one cycle.

Forms

Every encoding of KSHIFTRW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KSHIFTRW k, k, imm8 KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512VEX.LZ.66.0F3A.W1 30 /r ibAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, imm8
Skylake-SP, Ice Lake, Sapphire Rapids4 / 1p5
Zen 41 / 0.5FP1 FP2

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = low(k2, 16)                  # bits 63:16 of k2 are ignored: none
                                 # shifts in at bit 15
n = imm8.read()                  # 0 to 255, not masked
k1.write(v >> n)                 # bits 63:16 cleared

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KSHIFTRW k, k, imm8
kexplicitwrite
kexplicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KSHIFTRW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kshiftri_mask16 __mmask16 _kshiftri_mask16(__mmask16 A, const unsigned int I)

KSHIFTRW k, k, imm8 VEX.LZ -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512F_KOPW

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-525 (KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.