KTESTB instruction (AVX10.1)

KTESTB sets the flags from the low 8 bits of two mask registers and writes no register: ZF when their AND is zero, CF when the second ANDed with the inverted first is zero, and OF, SF, AF and PF cleared. KTESTW describes the test and its two questions, “no element in common” and “a subset”; KTESTB asks them of eight-element masks, the masks of a ZMM register of doubles or quadwords, or of a YMM register of doublewords. Like KTESTW and KORTESTB, it came with AVX512DQ; KTESTD and KTESTQ need AVX512BW.

Eight bits only

Bits 63:8 of both operands play no part. On Zen 5, two masks whose low bytes were both zero set ZF and CF, although their upper bits overlapped widely; a K7 of all ones tested against 55h set CF and cleared ZF, since 55h has no bit outside K7. The difference from KTESTW shows with masks from elsewhere: a compare of eight elements clears the bits above 7 of its mask, but a mask built in a general-purpose register and moved in with KMOVW or KMOVD may carry more, which KTESTB ignores and KTESTW would not.

In compiled code

With GCC 14 and Clang 23 at -O2 and -mavx512f -mavx512dq, the test whether two compares of doubles share an element, written as (m1 & m2) != 0 on two results of _mm512_cmp_pd_mask, became, as for the 16-bit case:

in Clang, both compares and ktestb k0, k1, then SETNE;
in GCC, the second compare under the first one’s mask and KORTESTB of the result with itself.

With -mavx512f alone neither instruction exists, and neither compiler falls back on a 16-bit test of the 8-bit mask: both run the second compare under the first’s mask, move the mask to EAX with KMOVW and test AL. The intrinsics _ktestz_mask8_u8 and _ktestc_mask8_u8 give KTESTB with SETE or SETC (SETB in Clang’s spelling); GCC moves the arguments in with KMOVB, Clang with KMOVW.

The instruction table of AMD’s Zen 5 guide lists KTESTB, like KTESTW, as two macro-ops.

Forms

Every encoding of KTESTB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`KTESTB k, k` KTESTB_MASKmskw_MASKmskw_AVX512	`VEX.LZ.66.0F.W0 99 /r`	AVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`k, k`
Skylake-SP, Ice Lake, Sapphire Rapids	3 / 1p0
Zen 4	1 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = low(k1, 8)                   # bits 63:8 of both are ignored
b = low(k2, 8)
zf = (a & b) == 0                # no bit set in both
cf = (b & ~a) == 0               # every bit of b set in a too
of = sf = af = pf = 0

Run on AMD Zen 5 (EPYC 9645): 12 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`KTESTB k, k`
`k`	explicit	read
`k`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	0	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KTESTB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_ktestc_mask8_u8` `unsigned char _ktestc_mask8_u8(__mmask8 __A, __mmask8 __B)`	`KTESTB k, k` VEX.LZ -mavx512dq
`_ktestz_mask8_u8` `unsigned char _ktestz_mask8_u8(__mmask8 __A, __mmask8 __B)`	`KTESTB k, k` VEX.LZ -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512DQ_KOPB` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

AVX512DQ_KOPB

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Eight bits only#

In compiled code#