KTESTQ instruction (AVX10.1)

KTESTQ sets two flags from two 64-bit masks without writing a register: ZF when their AND is zero, CF when the second ANDed with the inverted first is zero, and OF, SF, AF and PF cleared. KTESTW describes the test and its two questions, “no element in common” and “a subset”; KTESTQ asks them of 64 elements, the masks of byte compares on ZMM registers, and needs AVX512BW like KORTESTQ. On Zen 5 the top bit counts like any other: ktestq k3, k4 with K3 = 8000000000000000h and K4 = 8000000000000001h cleared ZF, as bit 63 is in both, and CF, as bit 0 of K4 is outside K3; ktestq k2, k2 with only bit 63 set set CF and cleared ZF.

In compiled code

With GCC 14 and Clang 23 at -O2 and -march=x86-64-v4, the test whether two byte compares on ZMM registers match at a common position, (_mm512_cmpeq_epi8_mask(a, b) & _mm512_cmpeq_epi8_mask(a, c)) != 0, compiled as the 16-bit version does:

Clang: both compares, ktestq k0, k1 and SETNE;
GCC: the second compare under the first one’s mask and KORTESTQ of the result with itself.

The subset test (m2 & ~m1) == 0 got KTESTQ from Clang, but through ZF rather than CF: it computed the inverted mask directly with a not-equal compare, VPCMPNEQB, tested it against the other with KTESTQ and used SETE. GCC again ran the second compare under the first one’s mask and tested the result with KORTESTQ. The intrinsics _ktestz_mask64_u8 and _ktestc_mask64_u8 give KTESTQ in both, followed by SETE, or by SETC in GCC’s spelling and SETB in Clang’s.

The instruction table of AMD’s Zen 5 guide lists KTESTQ, like KORTESTQ, as two macro-ops.

Forms

Every encoding of KTESTQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`KTESTQ k, k` KTESTQ_MASKmskw_MASKmskw_AVX512	`VEX.LZ.NP.0F.W1 99 /r`	AVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`k, k`
Skylake-SP, Ice Lake, Sapphire Rapids	3 / 1p0
Zen 4	1 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = k1.read()
b = k2.read()
zf = (a & b) == 0                # no bit set in both
cf = (b & ~a) == 0               # every bit of b set in a too
of = sf = af = pf = 0

Run on AMD Zen 5 (EPYC 9645): 12 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`KTESTQ k, k`
`k`	explicit	read
`k`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	0	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KTESTQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_ktestc_mask64_u8` `unsigned char _ktestc_mask64_u8(__mmask64 __A, __mmask64 __B)`	`KTESTQ k, k` VEX.LZ -mavx512bw
`_ktestz_mask64_u8` `unsigned char _ktestz_mask64_u8(__mmask64 __A, __mmask64 __B)`	`KTESTQ k, k` VEX.LZ -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512BW_KOPQ` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

AVX512BW_KOPQ

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

In compiled code#