KTESTW instruction (AVX10.1)

KTESTW sets two flags from two 16-bit masks without writing a register: ZF when their AND is zero, so that no element is selected by both, and CF when the second ANDed with the inverted first is zero, so that every element the second selects is selected by the first as well. OF, SF, AF and PF are cleared. It is PTEST for mask registers, and the bits above 15 of both operands play no part.

A later arrival

KTESTW is not part of AVX-512F. It came with AVX512DQ, together with the byte form KTESTB, and KTESTD and KTESTQ need AVX512BW. A processor with only AVX-512F, such as Knights Landing, has KORTESTW but no KTESTW: there, testing the AND of two masks takes a KANDW first.

In compiled code

With GCC 14 and Clang 23 at -O2 and -mavx512f -mavx512dq, the test whether two compares select a common element, (_mm512_cmpeq_epi32_mask(a, b) & _mm512_cmpeq_epi32_mask(a, c)) != 0, compiled two ways:

Clang: both compares and ktestw k0, k1, then SETNE;
GCC: the second compare under the first’s mask, which leaves the AND in one register, then KORTESTW of it with itself.

The subset test that CF answers, (m2 & ~m1) == 0, got KTESTW from neither compiler: Clang computed it in general-purpose registers and GCC inverted one mask and used a masked compare. The intrinsics _ktestz_mask16_u8 and _ktestc_mask16_u8 give KTESTW in both, followed by SETE, or by SETC in GCC’s spelling and SETB in Clang’s, which are one instruction.

The instruction table of AMD’s Zen 5 guide lists KTESTW, like KORTESTW, as two macro-ops. The cases recorded on Zen 5 include a mask tested against itself, which sets CF and leaves ZF clear unless the mask is zero.

Forms

Every encoding of KTESTW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`KTESTW k, k` KTESTW_MASKmskw_MASKmskw_AVX512	`VEX.LZ.NP.0F.W0 99 /r`	AVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`k, k`
Skylake-SP, Ice Lake, Sapphire Rapids	3 / 1p0
Zen 4	1 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = low(k1, 16)                  # bits 63:16 of both are ignored
b = low(k2, 16)
zf = (a & b) == 0                # no bit set in both
cf = (b & ~a) == 0               # every bit of b set in a too
of = sf = af = pf = 0

Run on AMD Zen 5 (EPYC 9645): 12 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`KTESTW k, k`
`k`	explicit	read
`k`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	0	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KTESTW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_ktestc_mask16_u8` `unsigned char _ktestc_mask16_u8(__mmask16 __A, __mmask16 __B)`	`KTESTW k, k` VEX.LZ -mavx512dq
`_ktestz_mask16_u8` `unsigned char _ktestz_mask16_u8(__mmask16 __A, __mmask16 __B)`	`KTESTW k, k` VEX.LZ -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512DQ_KOPW` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

AVX512DQ_KOPW

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

A later arrival#

In compiled code#