x86-64.net

Instruction

KUNPCKBW

Joins the low 8 bits of two masks into a 16-bit mask, the second source forming the low half.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KUNPCKBW builds a 16-bit mask from two 8-bit ones: the low byte of its last operand becomes bits 7:0 of the result, the low byte of the middle operand bits 15:8, and bits 63:16 of the destination are cleared. The order is the trap. In kunpckbw k1, k2, k3 the operand written first after the destination supplies the high half, the order in which a number is written, high part first; the intrinsic _mm512_kunpackb(a, b) keeps that order, a giving the high byte. The cases recorded on Zen 5 also show that only the low byte of each source counts: a source of FFFFFFFFFFFFFF01h contributes 01h.

Two compares of doubles, one mask of singles

A compare of eight doubles, as in a ZMM register, writes an 8-bit mask. Code that compares two such registers and then works on sixteen singles or doublewords, for example after converting the doubles, needs both masks in one. With GCC 14 and Clang 23 at -O2 and -mavx512f:

  • _mm512_kunpackb(hi, lo) on the two compare results is KUNPCKBW in both compilers;
  • written in plain C as lo | (hi << 8), it is KUNPCKBW in Clang only. GCC moves both masks to general-purpose registers, shifts, ORs and moves the result back with KMOVW.

KUNPCKBW is part of AVX-512F. KUNPCKWD and KUNPCKDQ, which join the 16-bit and 32-bit masks of byte and word elements, need AVX512BW. The instruction table of AMD’s Zen 5 guide lists KUNPCKBW as one macro-op with a latency of one cycle.

Forms

Every encoding of KUNPCKBW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KUNPCKBW k, k, k KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512VEX.L1.66.0F.W0 4B /rAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, k
Skylake-SP, Ice Lake, Sapphire Rapids4 / 1p5
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.b[0] = k3.b[0]                # the low half from the last operand
k1.b[1] = k2.b[0]
# bits 63:16 of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KUNPCKBW k, k, k
kexplicitwrite
kexplicitread
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KUNPCKBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm512_kunpackb __mmask16 _mm512_kunpackb(__mmask16 __A, __mmask16 __B)

KUNPCKBW k, k, k VEX.L1 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512F_KOPW

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-529 (KUNPCKBW/KUNPCKWD/KUNPCKDQ)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.