x86-64.net

Instruction

KUNPCKDQ

Joins the low 32 bits of two masks into a 64-bit mask, the second source forming the low half.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KUNPCKDQ builds a 64-bit mask from two 32-bit ones: the low 32 bits of its last operand become bits 31:0 of the result and the low 32 bits of the middle operand bits 63:32. It is the widest of the three unpacks and needs AVX512BW, as KUNPCKWD does; KUNPCKBW explains the operand order, high half first, and the intrinsic that keeps it, here _mm512_kunpackd(hi, lo). Two compares of 32 words on ZMM registers give two such halves, and the result serves 64 bytes.

Recorded on Zen 5

  • Only the low halves. kunpckdq k1, k2, k3 with K2 = 1DDA522655555555h and K3 = FFFFFFFFAAAAAAAAh gave 55555555AAAAAAAAh: the upper half of each source played no part.
  • One register twice. kunpckdq k7, k7, k7 repeated the low half of K7 in both halves, 6725547C6725547Ch.
  • K0 is a register here. kunpckdq k6, k7, k0 read K0, whose low half was zero, and kunpckdq k0, k4, k5 wrote FFFFFFFFh to K0.

In compiled code

With GCC 14 and Clang 23 at -O2 and -march=x86-64-v4, _mm512_kunpackd of two word compares is KUNPCKDQ in both, also when the result becomes the write mask of a byte move. Written in C as ((__mmask64)hi << 32) | lo, it is KUNPCKDQ in Clang only; GCC moves both masks to general-purpose registers with KMOVQ, shifts and ORs them there, as it does for KUNPCKBW.

AMD’s Zen 5 latency spreadsheet gives KUNPCKDQ one cycle and two per cycle on pipes FP0 and FP3, as KUNPCKBW.

Forms

Every encoding of KUNPCKDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KUNPCKDQ k, k, k KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512VEX.L1.NP.0F.W1 4B /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, k
Skylake-SP, Ice Lake, Sapphire Rapids4 / 1p5
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.d[0] = k3.d[0]                # the low half from the last operand
k1.d[1] = k2.d[0]

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KUNPCKDQ k, k, k
kexplicitwrite
kexplicitread
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KUNPCKDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm512_kunpackd __mmask64 _mm512_kunpackd(__mmask64 __A, __mmask64 __B)

KUNPCKDQ k, k, k VEX.L1 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512BW_KOPQ

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-529 (KUNPCKBW/KUNPCKWD/KUNPCKDQ)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.