x86-64.net

Instruction

KXNORQ

Computes the bitwise XNOR of two 64-bit masks.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

KXNORQ XORs all 64 bits of two mask registers, inverts the result and writes it to a third: a bit is 1 where the two sources agree. It is the AVX512BW form of KXNORW, for masks with one bit per byte of a ZMM register; KXNORW’s page explains its main use, all ones from any register, and KXNORB shows that K0 is an ordinary operand here.

Recorded on Zen 5

  • All ones from one register. kxnorq k5, k6, k6 and kxnorq k7, k7, k7 gave FFFFFFFFFFFFFFFFh from registers of random bits.
  • Disagreement gives zero. 5555555555555555h against AAAAAAAAAAAAAAAAh gave 0, and AAAAAAAAAAAAAAAAh against all ones gave AAAAAAAAAAAAAAAAh, the bits where both are 1.
  • All 64 bits. 833C54276BE4B998h against 0E81A79B52069367h gave 72420C43C61DD500h.

In compiled code

With GCC 14 and Clang 23 at -O2 and -march=x86-64-v4, the bytes where two equality tests agree, ~(m1 ^ m2) of two _mm512_cmpeq_epi8_mask results used as a zero mask, are one KXNORQ in both, after two compares: VPCMPB with predicate 0 in GCC, VPCMPEQB in Clang. For _kxnor_mask64 of two __mmask64 arguments GCC moves them into mask registers with KMOVQ, and Clang uses XOR and NOT on RAX.

AMD’s Zen 5 latency spreadsheet gives KXNORQ one cycle and two per cycle on pipes FP0 and FP3, as KXNORW.

Forms

Every encoding of KXNORQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
KXNORQ k, k, k KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512VEX.L1.NP.0F.W1 46 /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelk, k, k
Skylake-SP, Ice Lake, Sapphire Rapids1 / 1p0
Zen 41 / 0.5FP2 FP3

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1.q[0] = ~(k2.q[0] ^ k3.q[0])   # 1 where the bits agree: all ones
                                 # when k2 and k3 are one register

Run on AMD Zen 5 (EPYC 9645): 11 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
KXNORQ k, k, k
kexplicitwrite
kexplicitread
kexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-K20

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to KXNORQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kxnor_mask64 __mmask64 _kxnor_mask64(__mmask64 __A, __mmask64 __B)

KXNORQ k, k, k VEX.L1 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512BW_KOPQ

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-530 (KXNORW/KXNORB/KXNORQ/KXNORD)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.